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authorBen Skeggs <bskeggs@redhat.com>2009-07-06 19:58:15 +1000
committerBen Skeggs <bskeggs@redhat.com>2009-07-06 20:17:44 +1000
commit0ba588cb75af67a644f51add35778925d4088cf9 (patch)
tree026fbccd03df25d40f5cc90b1b445d067e1babb7 /src/nv_setup.c
parent3e22547b6826ae741b168c4b3391b6ade56b4829 (diff)
Rip out vgaHW + more unused vars from NVRec
Diffstat (limited to 'src/nv_setup.c')
-rw-r--r--src/nv_setup.c177
1 files changed, 0 insertions, 177 deletions
diff --git a/src/nv_setup.c b/src/nv_setup.c
index ba4fbd7..9438106 100644
--- a/src/nv_setup.c
+++ b/src/nv_setup.c
@@ -22,142 +22,6 @@
#include "nv_include.h"
-/*
- * Override VGA I/O routines.
- */
-static void NVWriteCrtc(vgaHWPtr pVga, CARD8 index, CARD8 value)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
- VGA_WR08(ptr, pVga->IOBase + VGA_CRTC_INDEX_OFFSET, index);
- VGA_WR08(ptr, pVga->IOBase + VGA_CRTC_DATA_OFFSET, value);
-}
-static CARD8 NVReadCrtc(vgaHWPtr pVga, CARD8 index)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
- VGA_WR08(ptr, pVga->IOBase + VGA_CRTC_INDEX_OFFSET, index);
- return (VGA_RD08(ptr, pVga->IOBase + VGA_CRTC_DATA_OFFSET));
-}
-static void NVWriteGr(vgaHWPtr pVga, CARD8 index, CARD8 value)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- VGA_WR08(pNv->PVIO0, VGA_GRAPH_INDEX, index);
- VGA_WR08(pNv->PVIO0, VGA_GRAPH_DATA, value);
-}
-static CARD8 NVReadGr(vgaHWPtr pVga, CARD8 index)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- VGA_WR08(pNv->PVIO0, VGA_GRAPH_INDEX, index);
- return (VGA_RD08(pNv->PVIO0, VGA_GRAPH_DATA));
-}
-static void NVWriteSeq(vgaHWPtr pVga, CARD8 index, CARD8 value)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- VGA_WR08(pNv->PVIO0, VGA_SEQ_INDEX, index);
- VGA_WR08(pNv->PVIO0, VGA_SEQ_DATA, value);
-}
-static CARD8 NVReadSeq(vgaHWPtr pVga, CARD8 index)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- VGA_WR08(pNv->PVIO0, VGA_SEQ_INDEX, index);
- return (VGA_RD08(pNv->PVIO0, VGA_SEQ_DATA));
-}
-static void NVWriteAttr(vgaHWPtr pVga, CARD8 index, CARD8 value)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
- volatile CARD8 tmp;
-
- tmp = VGA_RD08(ptr, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
- if (pVga->paletteEnabled)
- index &= ~0x20;
- else
- index |= 0x20;
- VGA_WR08(ptr, VGA_ATTR_INDEX, index);
- VGA_WR08(ptr, VGA_ATTR_DATA_W, value);
-}
-static CARD8 NVReadAttr(vgaHWPtr pVga, CARD8 index)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
- volatile CARD8 tmp;
-
- tmp = VGA_RD08(ptr, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
- if (pVga->paletteEnabled)
- index &= ~0x20;
- else
- index |= 0x20;
- VGA_WR08(ptr, VGA_ATTR_INDEX, index);
- return (VGA_RD08(ptr, VGA_ATTR_DATA_R));
-}
-static void NVWriteMiscOut(vgaHWPtr pVga, CARD8 value)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- VGA_WR08(pNv->PVIO0, VGA_MISC_OUT_W, value);
-}
-static CARD8 NVReadMiscOut(vgaHWPtr pVga)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- return (VGA_RD08(pNv->PVIO0, VGA_MISC_OUT_R));
-}
-static void NVEnablePalette(vgaHWPtr pVga)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
- volatile CARD8 tmp;
-
- tmp = VGA_RD08(ptr, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
- VGA_WR08(ptr, VGA_ATTR_INDEX, 0x00);
- pVga->paletteEnabled = TRUE;
-}
-static void NVDisablePalette(vgaHWPtr pVga)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
- volatile CARD8 tmp;
-
- tmp = VGA_RD08(ptr, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
- VGA_WR08(ptr, VGA_ATTR_INDEX, 0x20);
- pVga->paletteEnabled = FALSE;
-}
-static void NVWriteDacMask(vgaHWPtr pVga, CARD8 value)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
- VGA_WR08(ptr, VGA_DAC_MASK, value);
-}
-static CARD8 NVReadDacMask(vgaHWPtr pVga)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
- return (VGA_RD08(ptr, VGA_DAC_MASK));
-}
-static void NVWriteDacReadAddr(vgaHWPtr pVga, CARD8 value)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
- VGA_WR08(ptr, VGA_DAC_READ_ADDR, value);
-}
-static void NVWriteDacWriteAddr(vgaHWPtr pVga, CARD8 value)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
- VGA_WR08(ptr, VGA_DAC_WRITE_ADDR, value);
-}
-static void NVWriteDacData(vgaHWPtr pVga, CARD8 value)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
- VGA_WR08(ptr, VGA_DAC_DATA, value);
-}
-static CARD8 NVReadDacData(vgaHWPtr pVga)
-{
- NVPtr pNv = (NVPtr)pVga->MMIOBase;
- volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
- return (VGA_RD08(ptr, VGA_DAC_DATA));
-}
-
static void nv4GetConfig (NVPtr pNv)
{
uint32_t reg_FB0 = nvReadFB(pNv, NV_PFB_BOOT_0);
@@ -220,37 +84,8 @@ void
NVCommonSetup(ScrnInfoPtr pScrn)
{
NVPtr pNv = NVPTR(pScrn);
- vgaHWPtr pVga = VGAHWPTR(pScrn);
uint16_t implementation = pNv->Chipset & 0x0ff0;
- /*
- * Override VGA I/O routines.
- */
- pVga->writeCrtc = NVWriteCrtc;
- pVga->readCrtc = NVReadCrtc;
- pVga->writeGr = NVWriteGr;
- pVga->readGr = NVReadGr;
- pVga->writeAttr = NVWriteAttr;
- pVga->readAttr = NVReadAttr;
- pVga->writeSeq = NVWriteSeq;
- pVga->readSeq = NVReadSeq;
- pVga->writeMiscOut = NVWriteMiscOut;
- pVga->readMiscOut = NVReadMiscOut;
- pVga->enablePalette = NVEnablePalette;
- pVga->disablePalette = NVDisablePalette;
- pVga->writeDacMask = NVWriteDacMask;
- pVga->readDacMask = NVReadDacMask;
- pVga->writeDacWriteAddr = NVWriteDacWriteAddr;
- pVga->writeDacReadAddr = NVWriteDacReadAddr;
- pVga->writeDacData = NVWriteDacData;
- pVga->readDacData = NVReadDacData;
- /*
- * Note: There are different pointers to the CRTC/AR and GR/SEQ registers.
- * Bastardize the intended uses of these to make it work.
- */
- pVga->MMIOBase = (CARD8 *)pNv;
- pVga->MMIOOffset = 0;
-
#ifndef XSERVER_LIBPCIACCESS
pNv->REGS = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
@@ -264,16 +99,6 @@ NVCommonSetup(ScrnInfoPtr pScrn)
pci_device_map_range(pNv->PciInfo, pNv->VRAMPhysical, 0x10000, PCI_DEV_MAP_FLAG_WRITABLE, (void *)&pNv->FB_BAR);
#endif /* XSERVER_LIBPCIACCESS */
- //pNv->PGRAPH = pNv->REGS + (NV_PGRAPH_OFFSET/4);
-
- /* 8 bit registers */
- pNv->PCIO0 = (uint8_t *)pNv->REGS + NV_PRMCIO0_OFFSET;
- pNv->PDIO0 = (uint8_t *)pNv->REGS + NV_PRMDIO0_OFFSET;
- pNv->PVIO0 = (uint8_t *)pNv->REGS + NV_PRMVIO0_OFFSET;
- pNv->PCIO1 = pNv->PCIO0 + NV_PRMCIO_SIZE;
- pNv->PDIO1 = pNv->PDIO0 + NV_PRMDIO_SIZE;
- pNv->PVIO1 = pNv->PVIO0 + NV_PRMVIO_SIZE;
-
pNv->alphaCursor = (pNv->NVArch >= 0x11);
pNv->twoHeads = (pNv->Architecture >= NV_ARCH_10) &&
@@ -284,8 +109,6 @@ NVCommonSetup(ScrnInfoPtr pScrn)
pNv->gf4_disp_arch = pNv->twoHeads && implementation != CHIPSET_NV11;
- pNv->fpScaler = pNv->FpScale && pNv->gf4_disp_arch;
-
/* nv30 and nv35 have two stage PLLs, but use only one register; they are dealt with separately */
pNv->two_reg_pll = (implementation == CHIPSET_NV31) ||
(implementation == CHIPSET_NV36) ||