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2019-05-07radeonsi: add config entry for Counter-Strike Global OffensiveTimothy Arceri1-0/+3
This fixes rendering issues with gun scopes which is rather important. Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100239 (cherry picked from commit 49025292fbbf285d4473d2c20a83b6c533a79d45)
2019-05-07draw: flush when setting stream-out targetsErik Faye-Lund1-0/+2
We need to re-prepare the middle-end state to pick up changes to this state to react correctly to pausing/resuming stream-out. So let's add a flush here. Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Fixes: ec8cbd79ac4 "draw/softpipe: EXT_transform_feedback support (v2)" Reviewed-by: Roland Scheidegger <sroland@vmware.com> (cherry picked from commit d84b85bc28d50182f77f2e42e3c14ccedd70715f)
2019-05-06mesa: Makefile.sources: Add nir_lower_fb_read.c to Makefile.sources listJohn Stultz1-0/+1
In commit a99c360a4630 (nir: add pass to lower fb reads), a new file was added that needs to also be added to the Makefile.sources list used by the Android and SCons build system. Cc: Rob Clark <robdclark@chromium.org> Cc: Emil Velikov <emil.l.velikov@gmail.com> Cc: Amit Pundir <amit.pundir@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Alistair Strachan <astrachan@google.com> Cc: Greg Hartman <ghartman@google.com> Cc: Tapani Pälli <tapani.palli@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Fixes: a99c360a463 ("nir: add pass to lower fb reads") Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: John Stultz <john.stultz@linaro.org> (cherry picked from commit c7f2145b4b1551d521de2303b0dc97b56a0e3907)
2019-05-06mesa: Makefile.sources: Add ir3_nir_lower_load_barycentric_at_sample/offset ↵John Stultz1-0/+2
to Makefile.sources In commit 2f0b9d22495 ("freedreno/ir3: lower load_barycentric_at_offset") a new file was added that needs to also be added to the Makefile.sources list used by Android and SCons build system. Cc: Rob Clark <robdclark@chromium.org> Cc: Emil Velikov <emil.l.velikov@gmail.com> Cc: Amit Pundir <amit.pundir@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Alistair Strachan <astrachan@google.com> Cc: Greg Hartman <ghartman@google.com> Cc: Tapani Pälli <tapani.palli@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Fixes: 2f0b9d22495 ("freedreno/ir3: lower load_barycentric_at_offset") Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: John Stultz <john.stultz@linaro.org> (cherry picked from commit d04f44a459b26e51c1b941b5790291795cb520d1)
2019-05-06mesa: android: freedreno: Fix build failure due to path changeJohn Stultz1-1/+1
The ir3_nir_trig.py file was moved in a previous commit, aa0fed10d3574 (freedreno: move ir3 to common location), so update the Android.gen.mk file to match. Cc: Rob Clark <robdclark@chromium.org> Cc: Emil Velikov <emil.l.velikov@gmail.com> Cc: Amit Pundir <amit.pundir@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Alistair Strachan <astrachan@google.com> Cc: Greg Hartman <ghartman@google.com> Cc: Tapani Pälli <tapani.palli@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Fixes: aa0fed10d35 ("freedreno: move ir3 to common location") Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: John Stultz <john.stultz@linaro.org> (cherry picked from commit c9358621276ae49162e58d4a16fe37abda6a347f)
2019-05-06mesa: android: freedreno: build libfreedreno_{drm,ir3} static libsAmit Pundir6-2/+131
Add libfreedreno_drm/ir3 to the build Cc: Rob Clark <robdclark@chromium.org> Cc: Emil Velikov <emil.l.velikov@gmail.com> Cc: Amit Pundir <amit.pundir@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Alistair Strachan <astrachan@google.com> Cc: Greg Hartman <ghartman@google.com> Cc: Tapani Pälli <tapani.palli@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Fixes: b4476138d5a ("freedreno: move drm to common location") Fixes: aa0fed10d35 ("freedreno: move ir3 to common location") Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Amit Pundir <amit.pundir@linaro.org> [jstultz: Tweaked to add extra ir3 files from master] Signed-off-by: John Stultz <john.stultz@linaro.org> (cherry picked from commit 88105375c978f9de82af8c654051e5aa16d61614)
2019-05-06radv: Implement cosited_even sampling.Bas Nieuwenhuizen2-2/+83
Apparently cosited_even was the required one instead of midpoint. This adds slight offset of 0.5 pixels to the coordinates (+ we need the image size to convert to normalized coords) Fixes: 91702374d5d "radv: Add ycbcr lowering pass." Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 5692351264de9000b59b5eaab6e41f5fd547248d)
2019-05-06radv: Disable subsampled formats.Bas Nieuwenhuizen1-1/+2
Broken on Polaris and since I discovered NV12 is not subsampled, but a 2-plane format I decided I don't really care. Work to do to re-enable: 1) Figure out which devices support it natively. 2) Write some software emulation for the others. Fixes: 52c1adda21b "radv: Add ycbcr format features." Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 5cbe12ad1b8934c932f19070044563b9f3b9ab21)
2019-05-06util/drirc: add workarounds for bugs in Doom 3: BFGTimothy Arceri1-0/+5
This makes the game playable on radeonsi. Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110143 (cherry picked from commit 1af72fa4d665b9847dff9b22d7a7dea01c0960c7)
2019-05-04freedreno: remove unused forward struct declaration19.1-branchpointRob Clark1-2/+0
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04panfrost/midgard: iabs cannot run on mulAlyssa Rosenzweig1-1/+1
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard: Lower mixed csel (NIR)Alyssa Rosenzweig2-12/+83
Basically, when the conditions of a csel diverge, we scalarize to avoid going into weird code paths during emit. We could be doing better, but this case can't occur organically from GLSL as far as I can, though it does fix lowered atan2. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard: Fix RA when temp_count = 0Alyssa Rosenzweig2-50/+70
A previous commit by Tomeu aborted RA early, which solves the memory corruption issue, but then generates an incorrect compile. This fixes that. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard: Fix integer selectionAlyssa Rosenzweig2-33/+10
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost: Support RGB565 FBOsAlyssa Rosenzweig4-29/+80
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard/disasm: Handle dest_override generalizedAlyssa Rosenzweig1-22/+68
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard/disasm: Stub out 64-bitAlyssa Rosenzweig1-5/+15
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard/disasm: Print 8-bit sourcesAlyssa Rosenzweig1-23/+43
This handles the usual case. 8-bit register access parallels 16-bit access, but with one major caveat: in 8-bit mode, only half of the register file is actually (directly) accessible as sources. In particular, for each 16-bit integer register (hrN), we can only index a *single* 8-bit integer (qrN), corresponding to the lower 8-bits. To get the upper 8-bits, it is required to do an explicit shift. For example, to add the bytes of a 16-bit integer hr0.x and get the result as an 8-bit qr0, you'd need to do something like: ilsr hr1.x, hr0.x, #8 iadd qr0.x, qr0.x, qr1.x This scheme diverges from 32-bit registers, in that both the upper and lower halves of a 32-bit register are individually accessible as a pair of half registers. For contrast, to add the lower and upper 16-bits of a 32-bit integer r0.x, you can just: iadd hr0.x, hr0.x, hr1.x Since hr1.x = upper 16-bit of r0.x. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard/disasm: Support 8-bit destinationAlyssa Rosenzweig1-18/+21
Meanwhile, we're forced to disable dest_override, since it's not yet clear how this interacts with other bitnesses (it'll likely need to be overhauled in any case). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard: Rename ilzcnt8 -> iclzAlyssa Rosenzweig2-2/+2
Per OpenCL. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard: Fix crash on unknown opAlyssa Rosenzweig1-2/+6
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard/disasm: Fill in .int modAlyssa Rosenzweig1-1/+1
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard/disasm: Extend print_reg to 8-bitAlyssa Rosenzweig1-15/+34
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard/disasm: Catch mask errorsAlyssa Rosenzweig1-0/+11
We silently ignored certain bits of the mask, which causes issues when disassembly 8/64-bit ops. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04panfrost/midgard: reg_mode_full -> reg_mode_32, etcAlyssa Rosenzweig3-16/+16
In preparation for 8-bit and 64-bit operands, let's not reinforce the 32-bit-centric biases in the ISA. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-04freedreno/a6xx: deduplicate a few linesRob Clark1-6/+0
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04freedreno: add ubwc_enabled helperRob Clark6-26/+28
Since it is dependent on the tile mode (ie. disabled for smaller mipmap levels), we should handle it a similar way to fd_resource_level_linear(). The code previously mostly did the right thing because the old helper took the tile mode. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04freedreno: move UBWC color offset to fd_resource_offset()Rob Clark7-18/+42
Best to keep it encapsulated in the helper which returns layer/level offset (and actually use that helper everywhere) rather than spreading the logic around the code. Also add a helper to find UBWC offset, to complete the encapsulation. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04freedreno/a6xx: buffer resources cannot be compressedRob Clark1-26/+5
Small cleanup. They are just an array of data and only ever linear/ uncompressed. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04freedreno: mark imported resources as validRob Clark1-0/+2
If someone is importing a buffer, we can't really know the state of it's contents, so assume it is valid. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04freedreno/a6xx: UBWC support for imagesRob Clark2-19/+57
There are still some fallbacks we'll need to handle before we can enable UBWC by default. I think we may need to fallback to uncompressed if image atomic operations are used. And we still need to sort out how to handle image and sampler views of compressed resources if the image/ sampler view is using a format that does not support compression. (I think the latter should hopefully be uncommon outside of deqp/piglit.) But at least this gets us to the point where supertuxkart works properly with UBWC enabled ;-) Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04freedreno/a6xx: UBWC fixesRob Clark2-11/+78
A few fixes that get UBWC working for the games/benchmarks where I noticed problems before (in particular and manhattan, and stk (modulo image support for UBWC when compute shaders are used for post-process effects): + fix the size of the UBWC meta buffer (ie, the offset to color pixel data) that is returned by ->fill_ubwc_buffer_sizes() + correct size/layout for 8 and 16 byte per pixel formats + limit the supported formats.. Note all formats that can be tiled can be compressed. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04freedreno: update generated headersRob Clark8-32/+58
Corrects tex state ubwc pitch/size Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04freedreno/a6xx: OUT_RELOC vs OUT_RELOCW fixesRob Clark1-3/+3
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04freedreno/ir3: remove assertRob Clark1-1/+0
Fixes dEQP-GLES31.functional.ubo.random.all_per_block_buffers.13 and .20 ca3eb5db665cbcc2de5a5d3158e3dc68f86e5822 went from silently truncating the constant state, which was also the wrong thing to do, to an assert. Which then showed up in a couple of dEQPs. Actually there is nothing wrong with larger constant file so just drop the assert. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-04spirv/cl: support vload/vstoreKarol Herbst1-0/+55
Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-04nir: Add nir_op_vec helperKarol Herbst3-22/+14
with that we can simplify code where nir vectors are created v2: merge both lines in nir_vec Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-04nir: Add a nir_builder_alu variant which takes an array of componentsKarol Herbst1-14/+36
v2: rename to nir_build_alu_src_arr Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-04vtn: handle bitcast with pointer src/destKarol Herbst3-29/+45
v2: use vtn_push_ssa and vtn_ssa_value Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-04mesa: Leave aliasing of vertex and generic0 attribute to the dlist code.Mathias Fröhlich1-4/+1
Now that dlist compilation again knows if it is inside glBegin/glEnd, we can leave the decision if aliasing should occur to the vertex attribute setter functions instead of doing that at glArrayElement time. Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04mesa: Correct the is_vertex_position decision for dlists.Mathias Fröhlich3-14/+28
We have to use _mesa_inside_dlist_begin_end instead of _mesa_inside_begin_end to see if we are inside a glBegin/glEnd block in case of display lists. So split the is_vertex_position function used in vertex attribute processing into a imm and dlist variant and use the appropriate _mesa_inside_begin_end variant. Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04mesa: Set CurrentSavePrimitive in vbo_save_NotifyBegin.Mathias Fröhlich1-0/+2
That seems to be lost somewhere. Is needed for correct outside begin/end detection in display list compilation. And is needed for correct aliasing in dlists restablished in the next changes. Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04mesa: Remove the _glapi_table argument from _mesa_array_element.Mathias Fröhlich3-17/+11
The value is now unused. Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04mesa: Constify static const array in api_arrayelt.cMathias Fröhlich1-1/+1
Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04mesa: Remove the now unused _NEW_ARRAY state change flag.Mathias Fröhlich6-23/+2
Is no longer used, so we have less occasions where NewState is non zero. Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04mesa: Rip out now unused gl_context::aelt_context.Mathias Fröhlich7-91/+0
Now this part of gl_context state is unused and can be removed. Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04mesa: Implement _mesa_array_element by walking enabled arrays.Mathias Fröhlich1-126/+58
In glArrayElement, use the bitmask trick to just walk the enabled vao arrays. This should be about equivalent in execution time to walk the prepare aelt_context list. Finally this will allow us to reduce the _mesa_update_state calls in a few patches. v2: Add comments. Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04mesa: Use glVertexAttrib*NV functions for fixed function attribs.Mathias Fröhlich1-157/+28
In the glArrayElement implementation, use glVertexAttrib*NV type functions for fixed function attributes. We do the same in display execution when the list is replayed using immediate mode attribute functions. Using a single set of function pointers enables to use a unified loop to walk the vertex array attributes. Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04mesa: Factor out index function that will have multiple use.Mathias Fröhlich1-11/+18
For access to glArrayElement methods factor out a function to get the table lookup index for normalized/integer/double access. The function will be used in the next patch at least twice. v2: Use vertex_format_to_index instead of NORM_IDX. Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-04nir: Add a SSA type gathering passJason Ekstrand4-0/+223
This new pass (which isn't even compile-tested) attempts to determine the ALU type of all the SSA values in a function impl. It takes a greedy approach and assigns intness or floatness to everything it thinks can possibly contain an int or a float. Some values will be labled as both int and float and some will be labled as neither and it is up to the caller to decide what to do with this information. However, for a "nice" shader where the original source contained no bit-casts and no implicit bit-casts were introduced by optimizations, there shouldn't be any overlap in the two sets save for the odd CSEd zero constant. Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
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