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2022-02-02radv: Handle SDMA for padding.22.0-branchpointBas Nieuwenhuizen1-15/+44
Also assert that nobody actually needs to chain an SDMA IB because we have not implemented non-PKT3 chaining. Fixes: ef40f2ccc29 ("radv/amdgpu: Fix handling of IB alignment > 4 words.") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5923 Tested-by: Mike Lothian <mike@fireburn.co.uk> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14781>
2022-02-02intel: Add missing dep of gen_*_header.py on utils.py.Emma Anholt2-0/+5
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725>
2022-02-02freedreno/isaspec: Add missing dep of encode.py/decode.py calls on isa.pyEmma Anholt2-0/+3
Fixes: #5921 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725>
2022-02-02anv: Add experimental support for VK_NV_mesh_shaderCaio Oliveira1-12/+49
Enable setting ANV_EXPERIMENTAL_NV_MESH_SHADER=1 environment variable. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02intel/dev: Enable Mesh Shading for DG2Caio Oliveira1-1/+2
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02anv: Put first few push constants directly into Task/Mesh InlineDataMarcin Ślusarz2-2/+12
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02anv: include ClipDistance array in mesh shader per-vertex outputMarcin Ślusarz1-0/+16
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02anv: tell the hardware about gl_[Clip|Cull]Distance in mesh shadersMarcin Ślusarz1-2/+2
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02anv: Implement indirect dispatch for Mesh pipelineMarcin Ślusarz2-5/+106
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02anv: Add support for UBOs, SSBOs and push constants in Mesh pipelineMarcin Ślusarz6-14/+98
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02anv: Add support for non-zero firstTask in vkCmdDrawMeshTasksNVMarcin Ślusarz1-2/+5
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02anv: Enable conditional rendering in vkCmdDrawMeshTasksNVMarcin Ślusarz1-1/+3
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02anv: Implement Mesh Shading pipelineCaio Oliveira6-27/+426
The Mesh pipeline is implemented as a variant of the regular (primitive) Graphics Pipeline. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02anv: Add boilerplate for VK_NV_mesh_shaderCaio Oliveira2-0/+69
Use minimum values for the properties. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02intel/common: Add helper for URB allocation in Mesh pipelineCaio Oliveira2-0/+103
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESHCaio Marcelo de Oliveira Filho2-0/+2
And corresponding value in XML. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02pan/va: Add ARM_shader_framebuffer_fetch asm testAlyssa Rosenzweig1-0/+34
This is a nontrivial chunk of code that makes for a nice dis/assembler test case (and caught a bug already...). Add it to the observatory. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Handle shift lanes in assemblerAlyssa Rosenzweig1-0/+6
Noticed in a program using ARM_shader_framebuffer_fetch. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Add lots of swizzle assembler testsAlyssa Rosenzweig1-0/+43
The swizzle handling in ISA.xml was broken in a bunch of place. Now that we've fixed these issues, let's add tons of tests to validate. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Add 2-channel 8-bit swizzles for conversionsAlyssa Rosenzweig4-6/+48
Instructions like V2S8_TO_V2S16 need a special 4-bit special selecting any two bytes. The definition is the same as Bifrost. Let's call this a half-swizzle since we need a name, and it is indeed half a swizzle... Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Vectorize 8->16-bit conversionsAlyssa Rosenzweig1-4/+4
Matches Bifrost, too. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Fix lane select for [US]_TO_[USF]32Alyssa Rosenzweig1-4/+13
The lane select is in bit 28, this is covered by the "16-bit swizzle" mode. However, the source type isn't inferred from the name in valhall.py, so explicitly annotate the source as 16-bit. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Fix MKVEC.v2i16 lane selectAlyssa Rosenzweig1-2/+2
The lanes are at bit 28 and bit 26 respectively. This matches the 16-bit "swizzle" encoding. In general the handling of widens/swizzles/lane/lanes on Valhall is rather confused but... one problem at a time. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Test LD_TILE assemblyAlyssa Rosenzweig1-0/+1
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Add missing fields to LD_TILEAlyssa Rosenzweig1-0/+2
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Add missing <clamp/> to V2F32_TO_V2F16Alyssa Rosenzweig1-0/+1
For parity with Bifrost. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02pan/va: Add .absolute bit to BRANCHZIAlyssa Rosenzweig1-2/+3
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
2022-02-02anv: Update VK_KHR_fragment_shading_rate for newer HWLionel Landwerlin13-87/+480
Per primitive & attachment shading rate support added. v2: Rebase on KHR_dynamic_rendering Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02anv/pass: rely on precomputed dynamic rendering pass/subpass moreLionel Landwerlin2-96/+94
For instance, the current code in genX_cmd_buffer.c assumes that the depth/stencil attachments & resolves will be at the end of all attachments, but that won't be the case anymore with fragment rate shading. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02anv: force primitive shading rate write in last geometry stageLionel Landwerlin1-0/+29
v2: Use new helper to check if stage supports variable shading rate setting v3: Update comment & iterate backward (Caio) Apply only to relevant platforms (Lionel) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02intel/compiler: add primitive rate output supportLionel Landwerlin3-7/+19
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02intel/compiler: add a new pass to lower shading rate into HW formatLionel Landwerlin5-0/+130
Rework: * Jason: Modernize brw_nir_lower_shading_rate_output: 1. Use nir_shader_instructions_pass() 2. Use *_imm builder helpers. 3. Use nir_intrinsic_base() instead of ->const_index[0] v2: Also lower loads (Caio) v3: Update stage check to trigger lowering (Caio) v4: Assert on != MESH (Caio) v5: Fixup instruction insertion (Caio) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02nir/builder: add ishl_imm helperLionel Landwerlin1-0/+12
v2: add (y >= x->bit_size) condition (Caio) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02isl: disable CPB surface compressionLionel Landwerlin2-0/+11
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02isl: add support for coarse pixel control surfacesLionel Landwerlin7-0/+201
Those surfaces are used as attachment to rendering passes and describe the rate of coarse pixel shading for the pass. v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley) v3: Drop unused macro (Nanley) s/isl_to_gen/isl_encode/ (Nanley) Remove pitch alignment 128B constraint already covered by tiling (Nanley) Move some asserts together (Nanley) v4: Disable miptail for now (Nanley) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02intel/dev: details CPS feature supportLionel Landwerlin2-1/+8
DG2 introduces per primitive coarse pixel settings (in stages preceding the PS shader) and also a control surface specifying the rate at through the resulting surface. v2: update comment (Caio) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02genxml: add new 3DSTATE_PS_EXTRA bitLionel Landwerlin1-0/+1
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02genxml: gen12.5 changes for CPSLionel Landwerlin1-14/+53
v2: Make genxml look more like BSpec (Caio) Fixup X_Focal/Y_Focal entries (Caio) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02compiler: add VARYING bit for primitive shading rateLionel Landwerlin1-0/+1
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02r300: replace recursive calls with loopsFilip Gawin1-31/+27
Recursive "loops" tend to be more difficult to follow and understand. Additionally iterative approach should be nicer for compiler. (Less to allocate on stack and easier to optimize) Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13226>
2022-02-02intel/isl: Add more PRM text for HiZ/STC requirementNanley Chery1-5/+8
Add text describing why HierarchicalDepthBufferEnable must be set along with SeparateStencilBufferEnable. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
2022-02-02intel/isl: Fix depth buffer TiledSurface programmingNanley Chery1-4/+2
The assert for the TiledSurface field caught a programming error, but with a segfault instead of the usual route of assert-failing. We only set this field when we have a depth surface, but we also need to set it when one isn't provided. Fix this issue and drop the assert. Fixes: b77d694223a ("intel/isl: Allow HiZ with Tile4/64 surfaces") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5950 Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
2022-02-02intel/isl: Simplify Z-buffer tiling config during emitNanley Chery1-3/+3
For SNB and prior, assert that the surface is Y-tiled and use constants when configuring the tiling parameters. This makes a follow-on commit clearer. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
2022-02-02venus: update venus-protocol to 1.3.204Chia-I Wu18-150/+11828
There should be no visible functional change. Although an unrelated change in the codegen replaced vn_info_extension_spec_version by vn_info_extension_get. We have to adapt to that. Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org> Reviewed-by: Ryan Neph <ryanneph@google.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14782>
2022-02-02r300/r600: Add drm-shim support.Emma Anholt4-0/+233
I was tired of swapping gpus around just to check shader-db results of MRs for these. I put it in src/amd since it doesn't make sense in either of r300 or r600. Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14809>
2022-02-02r300: Disable fp16 and int16 in swtcl vertex shaders.Emma Anholt1-0/+9
We already had them disabled for hwtcl, but in the swtcl case gallivm's param query would return (nir) support even though nir-to-tgsi couldn't handle it because TGSI doesn't do fp16/int16. Fixes: 7d2ea9b0edef ("r300: Request NIR shaders from mesa/st and use NIR-to-TGSI.") Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14809>
2022-02-01anv: Report the right conformance versionIván Briano2-1/+2
Fixes: df8ac77af80 ("anv: Advertise Vulkan 1.3") Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14827>
2022-02-01anv: Handle resolveImageLayout on dynamic renderingIván Briano1-2/+21
Fixes: 5d9e8bc9be6 ("anv: implement the meat of VK_KHR_dynamic_rendering") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5942 Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14812>
2022-02-01zink: ARB_sparse_texture_clampMike Blumenkrantz1-0/+1
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14813>
2022-02-01radv/winsys: fix missing buffer_make_resident() for the null winsysSamuel Pitoiset1-0/+8
With latest Fossilize everything should now be captured correctly but without this, all Fossilize databases that need VK_EXT_custom_border_color would just crash. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14821>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-27 00:04:38 +0000