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path: root/src/mesa/drivers/dri/i965/brw_clip_tri.c
AgeCommit message (Expand)AuthorFilesLines
2011-12-21i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.Eric Anholt1-9/+6
2011-12-07i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.Paul Berry1-3/+8
2011-10-18intel: Convert from GLboolean to 'bool' from stdbool.h.Kenneth Graunke1-2/+2
2011-09-06i965: clip: Convert computations to ..._to_offset() for clarity.Paul Berry1-1/+1
2011-09-06i965: clip: Modify brw_clip_tri_alloc_regs() to use the VUE map.Paul Berry1-2/+5
2011-09-06i965: clip: Move hpos_offest and ndc_offset into local functions.Paul Berry1-6/+11
2011-05-17i965: Move IF stack handling into the EU abstraction layer/brw_compile.Kenneth Graunke1-37/+29
2010-07-19i965: Reduce repeated calculation of the attribute-offset-in-VUE.Eric Anholt1-4/+1
2010-06-10mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul1-1/+1
2010-05-14i965: Set the correct provoking vertex for clipped first-mode trifans.Eric Anholt1-3/+17
2010-04-21intel: Clean up chipset name and gen num for IronlakeZhenyu Wang1-1/+1
2010-01-25Merge branch 'mesa_7_7_branch'Brian Paul1-1/+0
2010-01-22i965: Remove unnecessary headers.Vinson Lee1-1/+0
2009-12-22intel: Replace IS_965 checks with context structure usage.Eric Anholt1-1/+2
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt1-2/+3
2009-11-11i965: fix EXT_provoking_vertex supportRoland Scheidegger1-3/+9
2009-07-30i965: Postpone ff_sync message in CLIP kernel on IGDNGXiang, Haihao1-2/+6
2009-07-13i965: add support for new chipsetsXiang, Haihao1-3/+10
2009-02-26i965: fix for RHW workaroundXiang, Haihao1-20/+56
2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt1-1/+1
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from Makefile.te...Brian Paul1-4/+4
2008-08-21965: Fix incorrect backface cullingKrzysztof Czurylo1-10/+0
2008-07-08i965: official name for GM45 chipsetXiang, Haihao1-1/+1
2008-04-17Revert "[i965] renable regative rhw test"Xiang, Haihao1-7/+9
2008-01-31[i965] renable regative rhw testZou Nan hai1-9/+7
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao1-8/+9
2008-01-25i965: re-define the type of reg.loopcount.Xiang, Haihao1-1/+1
2007-09-27 fix ppracer and bzflag issue with clip optimizationZou Nan hai1-1/+0
2007-08-31 optimize 965 clipZou Nan hai1-4/+103
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt1-0/+467
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