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path: root/src/intel
AgeCommit message (Expand)AuthorFilesLines
2018-04-20anv/blorp: Do the gen11 BTI flushJason Ekstrand1-0/+14
2018-04-20i965/fs: retype offset_reg to UD at load_ssboJose Maria Casanova Crespo1-1/+1
2018-04-19nir: Offset vertex_id by first_vertex instead of base_vertexNeil Roberts2-7/+1
2018-04-19spirv: Lower BaseVertex to FIRST_VERTEX instead of BASE_VERTEXNeil Roberts2-4/+14
2018-04-19intel: Handle firstvertex in an identical way to BaseVertexAntia Puentes3-0/+8
2018-04-19intel/compiler: Add a uses_firstvertex flagNeil Roberts2-0/+5
2018-04-16anv,radv: Drop XML workarounds for VK_ANDROID_native_bufferJason Ekstrand1-6/+1
2018-04-13anv: fix number of planes for depth & stencilLionel Landwerlin2-1/+5
2018-04-12mesa: include mtypes.h lessMarek Olšák3-0/+3
2018-04-11blorp: Silence unused function warningsNanley Chery2-3/+3
2018-04-11vulkan: fix build issue on android (both anv/radv)Tapani Pälli1-2/+2
2018-04-10vulkan: Drop vk_android_native_buffer.xmlJason Ekstrand4-32/+16
2018-04-11intel/dev: Assert the number of slices is not zeroTopi Pohjolainen1-1/+1
2018-04-09anv/pipeline: Lower more constant initializers earlierJason Ekstrand1-7/+5
2018-04-10intel: aubinator: print out addresses of invalid instructionsLionel Landwerlin1-9/+14
2018-04-06intel/compiler: Explicitly cast register type in switchIan Romanick1-1/+1
2018-04-05anv: Add WSI support for the I915_FORMAT_MOD_Y_TILED_CCSJason Ekstrand2-19/+40
2018-04-05intel/tools: new intel_sanitize_gpu toolKevin Rogovin3-0/+459
2018-04-05anv: Make blorp update the clear color.Rafael Antognolli3-63/+66
2018-04-05anv: Use clear address for HiZ fast clears too.Rafael Antognolli3-3/+27
2018-04-05anv: Emit the fast clear color address, instead of value.Rafael Antognolli3-4/+70
2018-04-05anv: Add a helper to extract clear color from the attachment.Rafael Antognolli2-13/+21
2018-04-05intel/blorp: Update clear color state buffer during fast clears.Rafael Antognolli1-0/+48
2018-04-05intel/blorp: Only copy clear color when doing a resolve.Rafael Antognolli1-4/+9
2018-04-05intel/blorp: Add support for fast clear address.Rafael Antognolli1-5/+13
2018-04-05intel/isl: Add support to emit clear value address.Rafael Antognolli2-4/+23
2018-04-05intel: Use Clear Color struct size.Rafael Antognolli6-15/+35
2018-04-05intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2-0/+18
2018-04-05intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2-8/+6
2018-04-05genxml: Preserve fields that share dword space with addresses.Rafael Antognolli1-2/+6
2018-04-05anv/image: Do not override lower bits of dword.Rafael Antognolli2-15/+12
2018-04-04intel: compiler: silence compiler warningLionel Landwerlin1-0/+1
2018-04-03anv: Fix close(fd) before import issue in vkCreateDmaBufImageINTELKevin Strasser1-2/+2
2018-04-03intel: gen-decoder: print all dword a field belongs toLionel Landwerlin2-7/+9
2018-04-03intel: genxml: decode variable length MI_LRILionel Landwerlin10-0/+40
2018-04-03intel: gen-decoder: don't decode fields beyond a dword lengthLionel Landwerlin1-15/+26
2018-04-03intel: error_decode: add an option to decode all buffersLionel Landwerlin1-2/+7
2018-04-03intel: genxml: add preemption control instructionsLionel Landwerlin4-0/+26
2018-04-03nir+drivers: add helpers to get # of src/dest componentsRob Clark1-6/+5
2018-04-02anv/cmd_buffer: honor pending clear views for depth/stencil attachmentsIago Toral Quiroga1-1/+21
2018-04-02anv/cmd_buffer: consider multiview masks for tracking pending clear aspectsIago Toral Quiroga2-3/+96
2018-03-30intel/vec4: Set channel_sizes for MOV_INDIRECT sourcesJason Ekstrand1-1/+4
2018-03-29util: Add and use util_is_power_of_two_nonzeroIan Romanick1-2/+2
2018-03-29util: Move util_is_power_of_two to bitscan.h and rename to util_is_power_of_t...Ian Romanick4-8/+8
2018-03-28autotools: Include intel/dev/meson.build in tarballDylan Baker1-0/+1
2018-03-27intel/fs: Don't emit a des copy for image ops with has_dest == falseJason Ekstrand1-3/+6
2018-03-26intel/aubinator_error_decode: Decode more registers.Rafael Antognolli1-0/+12
2018-03-26intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli6-0/+139
2018-03-26intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli6-0/+114
2018-03-26intel/genxml: Add SC_INSTDONE register.Rafael Antognolli6-0/+140
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