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path: root/src/gallium/winsys/virgl
AgeCommit message (Expand)AuthorFilesLines
2019-06-11virgl: add virgl_drm_{alloc,free,clear}_res_listChia-I Wu1-17/+42
2019-06-11virgl: do not cache external resourcesChia-I Wu2-1/+10
2019-06-07virgl: Make VIRGL_BIND_STAGING resources cacheableAlexandros Frantzis2-2/+4
2019-06-07virgl: Deduplicate checks for resource cachingAlexandros Frantzis4-20/+14
2019-06-07virgl: Don't try to use cached resources for legacy fencesAlexandros Frantzis2-6/+12
2019-05-06virgl: export resource_is_busy from winsysChia-I Wu2-11/+14
2019-04-25virgl/drm: insert correct handles into the table. (v3)Dave Airlie1-1/+4
2019-04-25virgl/drm: handle flink name better.Dave Airlie2-20/+11
2019-04-25virgl/drm: cleanup buffer from handle creation (v2)Dave Airlie2-15/+13
2019-04-18virgl/vtest: bump up protocol version + support encoded transfersGurchetan Singh3-3/+12
2019-04-18virgl/vtest: wait after issuing a transfer getGurchetan Singh1-2/+3
2019-04-18virgl/vtest: modify sending and receiving data for shared memoryGurchetan Singh1-4/+35
2019-04-18virgl/vtest: receive and handle shared memory fdGurchetan Singh2-7/+55
2019-04-18virgl/vtest: plumb support for shared memoryGurchetan Singh3-6/+10
2019-04-18virgl/vtest: add utilities for receiving fdsGurchetan Singh1-0/+43
2019-04-18virgl/vtest: execute a transfer_get when flushing the front bufferGurchetan Singh1-22/+21
2019-04-15virgl: fix fence fd version checkChia-I Wu1-2/+2
2019-04-15virgl: introduce virgl_drm_fenceChia-I Wu2-45/+115
2019-04-15virgl: hide fence internals from the driverChia-I Wu2-28/+42
2019-04-15virgl: handle fence_server_sync in winsysChia-I Wu3-12/+25
2019-04-15Delete autotoolsDylan Baker2-69/+0
2019-04-02virgl: close drm fd when destroying virgl screen.Lepton Wu1-0/+1
2019-03-13virgl: use uint16_t mask instead of separate booleansGurchetan Singh2-80/+83
2019-02-27virgl/vtest: deprecate protocol version 1Gurchetan Singh4-43/+23
2019-02-15virgl: make winsys modifications for encoded transfersGurchetan Singh3-3/+16
2019-02-14drm-uapi: use local files, not system libdrmEric Engestrom1-1/+1
2019-01-03virgl/vtest: Use default socket name from protocol headerJakob Bornecrantz1-3/+1
2018-12-28virgl/vtest: fix front buffer flush with protocol version 0.Dave Airlie1-1/+1
2018-11-28virgl,vtest: Initialize return valueGert Wollny1-1/+1
2018-11-19virgl: fix vtest regression since fencing changes.Dave Airlie1-0/+1
2018-11-19virgl: Use file descriptor instead of un-allocated objectGert Wollny1-1/+1
2018-11-18virgl: Clean up fences commitRobert Foss3-3/+0
2018-11-16virgl: native fence fd supportRobert Foss4-6/+104
2018-11-02virgl/vtest-winsys: Use virgl version of bind flagsGert Wollny1-1/+1
2018-10-06virgl: Pass resource size and transfer offsetsTomeu Vizoso4-28/+208
2018-10-06virgl, vtest: Correct the transfer size calculationGert Wollny1-1/+3
2018-10-04virgl: Negotiate version with vtest serverTomeu Vizoso3-0/+64
2018-09-12winsys/virgl: avoid unintended behaviorErik Faye-Lund1-1/+1
2018-09-05winsys/virgl/vtest: Correct off-by-one error in resource allocationGert Wollny1-4/+9
2018-09-05winsys/virgl: Initialize value to silence valgrindGert Wollny1-1/+1
2018-09-05winsys/virgl: correct resource and handle allocation (v2)Gert Wollny1-5/+18
2018-07-24Revert "virgl: remove unused stride-arguments"Dave Airlie1-0/+6
2018-07-23virgl: remove unused stride-argumentsErik Faye-Lund1-6/+0
2018-07-10virgl/vtest: add support to vtest for new cap getting.Dave Airlie2-4/+28
2018-06-19virgl: Remove debugging left-oversTomeu Vizoso1-2/+0
2018-05-30gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*Dave Airlie1-6/+6
2018-04-23virgl: disable virgl when no 3D for virtio gpu.Lepton Wu1-0/+11
2018-03-15virgl: resize resource bo allocation if we need to.Dave Airlie2-4/+12
2018-03-05virgl: handle getting new capsets.Dave Airlie5-30/+28
2018-02-13virgl: Support v2 caps struct (v2)Stéphane Marchesin1-1/+37
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