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path: root/src/gallium/drivers
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2014-05-28i915g: Support B5G5R5A1 render targets and texturesStéphane Marchesin1-0/+2
2014-05-28i915g: Support R4G4B4A4 render targets and texturesStéphane Marchesin1-0/+2
2014-05-28i915g: Fix copy region codeStéphane Marchesin1-34/+14
This fixes a few issues with it, also cleans up the code.
2014-05-27nvc0/ir: use SM35 ISA with GK20AAlexandre Courbot3-7/+12
GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-27nvc0: add GK20A 3D classAlexandre Courbot2-1/+9
GK20A is mostly compatible with GK104, but features a new 3D class. Add it to the relevant header and use it when GK20A is detected. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-27radeon/vce: implement non-referenced framesLeo Liu2-3/+5
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2014-05-26i915g: Fix shader disasm codeStéphane Marchesin1-1/+0
This broke when I separated declarations/shader.
2014-05-26i915g: Fallback to sw for npot copiesStéphane Marchesin1-2/+3
i915g's npot support is incomplete, so let's not use it for copies. This fixes a bunch of piglit tests.
2014-05-26i915g: handle more formats in copyStéphane Marchesin3-11/+91
We can handle depth, luminance,... copies by simply replacing the format with a known format of the same bpp.
2014-05-26nvc0: implement clear_bufferTobias Klausmann1-0/+141
Provide an accelerated path for ARB_clear_buffer_object Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-26nvc0: revert mistaken logic to collapse color outputs to the beginningIlia Mirkin1-9/+4
In commit af38ef907, I added a "fix" to color outputs not being assigned correctly when sample mask was being output. This was totally wrong -- the color indices (i.e. "si" values) were the ones that were wrong. Undo that hunk. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-05-26freedreno/a3xx: texture fixesRob Clark1-1/+3
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-26freedreno: update generated headersRob Clark4-5/+7
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-26freedreno: few caps fixesRob Clark2-4/+8
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-23nv50: count wrapped textures towards the tex_obj countJoakim Sindholt1-0/+2
But don't count their size towards the allocated memory, since that belongs to whoever created it. Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-23nvc0: assert that we have vertex elements stateChristoph Bumiller1-0/+1
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-23nvc0: use PRIxPTR for sizeof()Christoph Bumiller1-1/+1
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-23nv50,nvc0: allow 15,16,30 bpp display formatsChristoph Bumiller1-4/+4
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-23nv50,nvc0: handle guard band definesChristoph Bumiller2-4/+16
[imirkin: moved default case out of switch] Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-05-23nv50/ir/tgsi: optimize KILChristoph Bumiller1-0/+5
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-23nv50/ir: fix lowering of predicated instructions (without defs)Christoph Bumiller1-1/+4
Note that predicated instructions with defs are still not supported because transformation to SSA doesn't handle them yet. Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-23nv50/ir/opt: fix constant folding with saturate modifierChristoph Bumiller1-1/+3
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-23nv50/ir/tgsi: TGSI_OPCODE_POW replicates its resultChristoph Bumiller1-1/+5
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-23nv50,nvc0: set constbufs dirty on pipe context switchChristoph Bumiller2-0/+5
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-23nv50: setup scissors on clear_render_target/depth_stencilChristoph Bumiller1-2/+18
[imirkin: add logic to also clear the "regular" scissors] Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-23nv50,nvc0: always pull out bufctx on context destructionChristoph Bumiller2-9/+7
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-21freedreno/a3xx: fix blend opcodeRob Clark8-54/+83
Seems the opcodes are slightly different from a2xx. Resync headers and move blend_func() helper into hw generation specific code. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-21freedreno/a3xx: fix depth/stencil gmem restoreRob Clark1-1/+1
We already multiply by bytes per pixel for this, so f3ba7611 broke mem2gmem for depth/stencil. Drop the now-redundant mutiply by cpp. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-21freedreno/a3xx: fix depth/stencil GMEM positioningRob Clark1-12/+18
In cases where there was no color buf bound, there were inconsistancies in register settings related to position of depth/stencil inside GMEM. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-21freedreno: update generated headersRob Clark4-5/+5
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-21freedreno: use OUT_RELOCW when buffer is writtenRob Clark1-4/+4
These aren't buffers we ever read back from CPU, so using incorrect reloc fxn wasn't really harming anything. But might as well be correct. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-21rbug: add missing pipe->blit() entrypointRob Clark1-0/+21
Signed-off-by: Rob Clark <robclark@freedesktop.org> Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2014-05-21nv50,nvc0: fix 3d blits with mipmap levelsIlia Mirkin2-11/+19
Make sure to normalize the z coordinates as well as the x/y ones when there are mipmaps present. Fixes 3d mipmap generation, which now uses the blit path. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.2" <mesa-stable@lists.freedesktop.org> Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-21nv50/ir: fix constant folding for OP_MUL subop HIGHIlia Mirkin1-4/+43
These instructions can come in either through IMUL_HI/UMUL_HI TGSI opcodes, or from OP_DIV constant folding. Also make sure that the constant foldings which delete the original instruction still get counted as having done something. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org> Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-21nv50/ir: fix s32 x s32 -> high s32 multiply logicIlia Mirkin2-11/+82
Retrieving the high 32 bits of a signed multiply is rather annoying. It appears that the simplest way to do this is to compute the absolute value of the arguments, and perform a u32 x u32 -> u64 operation. If the arguments' signs differ, then negate the result. Since there is no u64 support in the cvt instruction, we have the perform the 2's complement negation "by hand". This logic can come into use by the IMUL_HI instruction (very unlikely to be seen), as well as from constant folding of division by a constant. Fixes dolphin's divisions by 255. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org> Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-20freedreno: don't advertise texture arrays for nowRob Clark1-1/+1
I think a3xx and later should support (it is part of GLES3), but this isn't needed for the time being and still needs to be reversed. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-19freedreno/a3xx: shadow sampler supportRob Clark2-3/+46
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-19freedreno/a3xx/compiler: refactor trans_samp()Rob Clark1-47/+90
Split it up into some smaller fxns so it doesn't grow into a huge monster as we add things. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-19freedreno: update generated headersRob Clark4-4/+10
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-19llvmpipe: do IR counting for shader cache management after optimization.Roland Scheidegger1-2/+2
2ea923cf571235dfe573c35c3f0d90f632bd86d8 had the side effect of IR counting now being done after IR optimization instead of before. Some quick analysis shows that there's roughly 1.5 times more IR instructions before optimization than after, hence the effective shader cache size got quite a bit smaller. Could counter this with an increase of the instruction limit but it probably makes more sense to count them after optimizations, so move that code. Reviewed-by: Brian Paul <brianp@vmware.com>
2014-05-18nv50/ir: fix integer mul lowering for u32 x u32 -> high u32Ilia Mirkin1-3/+4
UNION appears to expect that all of its sources are conditionally defined. Otherwise it inserts an unpredicated mov instruction which overwrites the desired result. This fixes tests that use UMUL_HI, and much less directly, unsigned integer division by a constant, which uses this functionality in a peephole pass. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org> Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-18nv50/ir: make sure that texprep/texquerylod's args get coalescedIlia Mirkin1-0/+2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.2" <mesa-stable@lists.freedesktop.org> Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
2014-05-18freedreno/a3xx: use util_format_compose_swizzles()Rob Clark1-9/+9
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-18freedreno/a3xx/compiler: 1D texturesRob Clark1-4/+25
Gallium already gives us height==1 for these, so the texture state is already setup correctly to emulate 1D textures as a Nx1 2D texture. We just need to supply the .y coord. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-18freedreno: fix capsRob Clark1-2/+2
In particular, we want mesa to emulate primitive restart for us. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-18freedreno: fix index buffer offsetRob Clark1-1/+1
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-16freedreno/a3xx: add sRBG texture supportRob Clark2-0/+15
That was easy. Turns out it is just a matter of setting one bit. Enable sampling from sRGB texture, and therefore enable GL 2.1 :-) Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-16freedreno: update generated headersRob Clark4-20/+21
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-16gallivm: give more verbose names to modulesRoland Scheidegger7-16/+21
When we had just one module "gallivm" was an appropriate name. But now we have modules containing all functions for a particular variant, so give it a corresponding name (this is really just for helping debugging). Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-05-15gallium/radeon: link in libradeon.la at target levelEmil Velikov3-20/+8
It makes more sense to link the core and common parts of the driver as the target is build. Additionally this will help us drop duplicating symbols for targets that static link mulitple pipe-drivers. Only egl-static needs that currently with more to come. To simplify things a bit add HAVE_GALLIUM_RADEON_COMMON variable. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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