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path: root/src/gallium/drivers/swr/swr_shader.cpp
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2020-02-05gallium/swr: Fix gcc 4.8.5 compile errorKrzysztof Raszkowski1-6/+5
Stop using C++14 feature so it can be compile on default centos7 gcc compiler. Reviewed-by: Jan Zielinski <jan.zielinski@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3679> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3679>
2020-01-24gallium/swr: implementation of tessellation shaders compilationJan Zielinski1-6/+1441
TCS and TES shaders compilation mechanisms in SWR and state management implementation. Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com> Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com> Acked-by: Roland Scheidegger <sroland@vmware.com> Acked-by: Dave Airlie <airlied@redhat.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484>
2019-12-12swr: Fix build with llvm-10.0.Vinson Lee1-0/+4
Fix build error after llvm-10.0 commit ("1b2842bf902a [Alignment][NFC] CreateMemSet use MaybeAlign"). ../src/gallium/drivers/swr/swr_shader.cpp: In member function ‘void (* BuilderSWR::CompileGS(swr_context*, swr_jit_gs_key&))(HANDLE, HANDLE, SWR_GS_CONTEXT*)’: ../src/gallium/drivers/swr/swr_shader.cpp:738:65: error: no matching function for call to ‘BuilderSWR::MEMSET(llvm::Value*&, llvm::Constant*, int, long unsigned int)’ MEMSET(pStream, C((char)0), VERTEX_COUNT_SIZE + CONTROL_HEADER_SIZE, sizeof(float) * KNOB_SIMD_WIDTH); ^ In file included from ../src/gallium/drivers/swr/rasterizer/jitter/builder.h:163:0, from ../src/gallium/drivers/swr/swr_shader.cpp:43: src/gallium/drivers/swr/rasterizer/jitter/gen_builder.hpp:51:11: note: candidate: llvm::CallInst* SwrJit::Builder::MEMSET(llvm::Value*, llvm::Value*, uint64_t, llvm::MaybeAlign, bool, llvm::MDNode*, llvm::MDNode*, llvm::MDNode*) CallInst* MEMSET(Value *Ptr, Value *Val, uint64_t Size, MaybeAlign Align, bool isVolatile = false, MDNode *TBAATag = nullptr, MDNode *ScopeTag = nullptr, MDNode *NoAliasTag = nullptr) ^ src/gallium/drivers/swr/rasterizer/jitter/gen_builder.hpp:51:11: note: no known conversion for argument 4 from ‘long unsigned int’ to ‘llvm::MaybeAlign’ In file included from ../src/gallium/drivers/swr/rasterizer/jitter/builder.h:163:0, from ../src/gallium/drivers/swr/swr_shader.cpp:43: src/gallium/drivers/swr/rasterizer/jitter/gen_builder.hpp:56:11: note: candidate: llvm::CallInst* SwrJit::Builder::MEMSET(llvm::Value*, llvm::Value*, llvm::Value*, llvm::MaybeAlign, bool, llvm::MDNode*, llvm::MDNode*, llvm::MDNode*) CallInst* MEMSET(Value *Ptr, Value *Val, Value *Size, MaybeAlign Align, bool isVolatile = false, MDNode *TBAATag = nullptr, MDNode *ScopeTag = nullptr, MDNode *NoAliasTag = nullptr) ^ src/gallium/drivers/swr/rasterizer/jitter/gen_builder.hpp:56:11: note: no known conversion for argument 4 from ‘long unsigned int’ to ‘llvm::MaybeAlign’ Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-11-14util: Move gallium's PIPE_FORMAT utils to /util/format/Eric Anholt1-1/+1
To make PIPE_FORMATs usable from non-gallium parts of Mesa, I want to move their helpers out of gallium. Since u_format used util_copy_rect(), I moved that in there, too. I've put it in a separate directory in util/ because it's a big chunk of related code, and it's not clear to me whether we might want it as a separate library from libmesa_util at some point. Closes: #1905 Acked-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-08gallium/swr: Fix GS invocation issuesKrzysztof Raszkowski1-2/+7
- Fixed proper setting gl_InvocationID. - Fixed GS vertices output memory overflow. Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-10-29gallium/swr: Enable GL_ARB_gpu_shader5: multiple streamsKrzysztof Raszkowski1-8/+67
Added support for geometry shader multiple streams (part of GL_ARB_gpu_shader5 extension). Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-10-15gallivm/draw/swr: make the gs_iface not depend on tgsi.Dave Airlie1-42/+42
This gs_iface doesn't seem to require a dependence on the tgsi context, except for the swr end prim code. This refactors the API to include all the info that the swr code needs in the interface rather than having to dig it out of the struct inheritance. This is a precursor to adding NIR support to llvmpipe. Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-09-17swr: Limit DEBUG workaround to LLVM < 7Michel Dänzer1-1/+8
As of version 7, LLVM uses LLVM_DEBUG instead of just DEBUG. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-09-06swr: replace major llvm version checks with LLVM_VERSION_MAJOREric Engestrom1-3/+4
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2019-09-02swr: Fix make_unique build error.Vinson Lee1-3/+3
swr_shader.cpp: In function ‘void (* swr_compile_gs(swr_context*, swr_jit_gs_key&))(HANDLE, HANDLE, SWR_GS_CONTEXT*)’: swr_shader.cpp:732:44: error: ‘make_unique’ was not declared in this scope ctx->gs->map.insert(std::make_pair(key, make_unique<VariantGS>(builder.gallivm, func))); ^~~~~~~~~~~ Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-08-30swr/rasterizer: Fix GS attributes processingJan Zielinski1-4/+3
Input to GS is just a set of attributes, so remove explicit setup of 'position' which is meaningless for GS input processing. Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-08-29swr/rasterizer: Enable ARB_fragment_layer_viewportJan Zielinski1-1/+16
Added loading gl_Layer and gl_ViewportIndex variables to Pixel Shader context. Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-07-25gallium: fix windows build from params change.Dave Airlie1-3/+6
This is why we can't have nice things. I'm sure there's someway to do this with {0} but I really don't have time for that. Fixes: 2631fd3b0bf ("gallivm: rework lp_build_tgsi_soa to take a struct") Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-24gallivm: rework lp_build_tgsi_soa to take a structDave Airlie1-39/+39
The parameters were getting messy and I have to add a few more for compute shaders, so clean it up before proceeding. Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-18swr/rast: Refactor memory API between rasterizer core and swrJan Zielinski1-0/+1
This commit cleans up API between the core of the rasterizer and swr. Some formatting changes are also done. Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-07-07gallivm: add ssbo pointers to the soa build api.Dave Airlie1-3/+6
Need to pass ssbo + ssbo size pointers just like constants. Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-03swr/swr: Enable ARB_viewport_arrayJan Zielinski1-0/+3
The rasterizer core supported ARB_viewport_array, but the swr layer connecting core to Gallium state tracker only allowed one viewport. We add support for multiple viewports to swr layer. Reviewed-by: Alok Hota <alok.hota@intel.com>
2018-05-25swr/rast: Removed superfluous JitManager argument from passesAlok Hota1-1/+1
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Optimize late/bindless JIT of samplersGeorge Kyriazis1-0/+9
Add per-worker thread private data to all shader calls Add per-worker sampler cache and jit context Add late LoadTexel JIT support Add per-worker-thread Sampler / LoadTexel JIT Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr: add x86 lowering pass to fragment shaderGeorge Kyriazis1-0/+7
Needed because some FP paths (namely stipple) use gather intrinsics that now need to be lowered to x86. v2: fix typo in commit message Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-03-06tgsi/scan: use wrap-around shift behavior explicitly for file_maskRoland Scheidegger1-1/+1
The comment said it will only represent the lowest 32 regs. This was not entirely true in practice, since at least on x86 you'll get masked shifts (unless the compiler could recognize it already and toss it out). It turns out this actually works out alright (presumably noone uses it for temp regs) when increasing max sampler views, so make that behavior explicit. Albeit it feels a bit hacky (but in any case, explicit behavior there is better than undefined behavior). Reviewed-by: Jose Fonseca <jfonseca@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2018-01-19swr: Support simd16 vertex shadersGeorge Kyriazis1-12/+30
Supporting simd16 vertex shaders involves packing the output of the fetch shader appropriately, especially the vertexID buffers that have to be formatted in one simd16 register, needed by the VS. As part of this support, we needed to remove the 2nd JitManager, since it was not accounting for vector width correctly. USE_SIMD16_SHADERS is also split into two defines. The additional one (USE_SIMD16_VS) controls the width of the vertex shader (VS), while the original one (USE_SIMD16_SHADERS) controls overall front end width. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-10swr: Handle indirect indices in GSGeorge Kyriazis1-8/+39
BuilderSWR::swr_gs_llvm_fetch_input() (and consequently swr_gs_llvm_fetch_input()), did not handle the case where is_vindex_indirect or is_aindex_direct is set. Implement it, using the code in draw_llvm.c as a guideline. Fixes the following piglit tests: dynamic_input_array_index (crash) gs-input-array-vec4-index-rd vs-output-array-vec4-index-wr-before-gs Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-11-20swr/rast: Simplify GATHER* jit builder apiTim Rowley1-1/+1
General cleanup, and prep work for possibly moving to llvm masked gather intrinsic. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-11swr: simd16 shaders work in progressTim Rowley1-2/+12
Start building vertex shaders as simd16. Disabled by default, set USE_SIMD16_SHADERS in knobs.h to experiment. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-25swr/rast: New GS state/context APITim Rowley1-98/+85
One piglit regression, which was a false pass: spec@glsl-1.50@execution@geometry@dynamic_input_array_index Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-07-27swr: fix transform feedback logicGeorge Kyriazis1-1/+31
The shader that is used to copy vertex data out of the vs/gs shaders to the user-specified buffer (streamout or SO shader) was not using the correct offsets. Adjust the offsets that are used just for the SO shader: - Make sure that position is handled in the same special way as in the vs/gs shaders - Use the correct offset to be passed in the core - consolidate register slot mapping logic into one function, since it's been calculated in 2 different places (one for calcuating the slot mask, and one for the register offsets themselves Also make room for all attibutes in the backend vertex area. Fixes: - all vtk GL2PS tests - 18 piglit tests (16 ext_transform_feedback tests, arb-quads-follow-provoking-vertex and primitive-type gl_points v2: - take care of more SGV slots in slot mapping logic - trim feState.vsVertexSize - fix GS interface and incorporate GS while calculating vsVertexSize Note that vsVertexSize is used in the core as the one parameter that controls vertex size between all stages, so it has to be adjusted appropriately for the whole vs/gs/fs pipeline. Also note that GS and SO is not fully implemented. This will be addressed later. fixes: - fixes total of 20 piglit tests CC: 17.2 <mesa-stable@lists.freedesktop.org> Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-30swr/rast: Support dynamically sized vertex layoutTim Rowley1-0/+2
Each shader stage state (VS, TS, GS, SO, BE/CLIP) now has a vertexAttribOffset to specify the offset to the start of the general attribute section of the incoming verts for that stage. It is up to the driver to set this up correctly based on the active stages. All the shader stages use this value instead of VERTEX_ATTRIB_START_SLOT to offset to the incoming attributes. Only the vertex shader stage supports dynamic layout output currently. The other stages continue to expect the output to be the fixed layout slots as before. Will be enabling GS next. Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
2017-06-16swr/rast: Fix read-back of viewport array indexTim Rowley1-2/+0
Binner/clipper read viewport array index from the vertex header as needed. Move viewport state to BACKEND_STATE. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16swr/rast: Fix read-back of render target array indexTim Rowley1-1/+0
The last FE stage can emit render target array index. Currently we only check to see if GS is emitting it. Moved the state to BACKEND_STATE and plumbed the driver to set it. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16swr/rast: Rework attribute layoutTim Rowley1-21/+57
Move fixed attributes to the top and pack single component SGVs. WIP to support dynamically allocated vertex size. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16swr/rast: Remove explicit primitive id slot in the vertex layoutTim Rowley1-12/+9
- Remove any special casing in the PS stage when primitive ID is input. Treat as a normal attribute that must be set up properly in the FE linkage. - Remove primitive id from the PS_CONTEXT and TRI_FLAGS Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-30swr/rast: SIMD16 FE - interleaved simdvertex output in GSTim Rowley1-3/+26
Eliminates conversion copies on GS output from simdvertex to simd16vertex. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-05-17swr: don't use AttributeSet with llvm >= 5Tim Rowley1-15/+21
This change fixes the build break with llvm-svn. r301981 of llvm-svn made add/remove of function attributes use AttrBuilder instead of AttributeList. Tested with llvm-3.9, llvm-4.0, llvm-svn. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-19swr: simd16 vs workTim Rowley1-5/+25
Build VS with alternating output for the current simd16 fe double-pump of a simd8 shader. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-14swr: Add polygon stipple supportGeorge Kyriazis1-6/+50
Add polygon stipple functionality to the fragment shader. Explicitly turn off polygon stipple for lines and points, since we do them using tris. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-07swr: fix unused variable warningsTim Rowley1-1/+0
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-03-28swr: fix llvm-5.0.0 build bustageTim Rowley1-9/+15
Handle rename of llvm AttributeSet to AttributeList in the same fashion as ac_llvm_helper.cpp. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-03-20swr: [rasterizer] Cleanup naming of codegen filesTim Rowley1-2/+2
All template files and generated files are prefixed with gen_. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-03-15swr: support layer output in geometry shadersIlia Mirkin1-0/+2
This makes bin/gl-3.2-layered-rendering-gl-layer-render fail only with 2DMS_ARRAY, which is expected given the lackluster MSAA support. However all the regular types pass. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-03-08swr: s/unsigned/enum pipe_shader_type/Brian Paul1-1/+1
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-03-05swr: implement geometry shadersTim Rowley1-5/+470
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-03-02swr: fix crash in swr_update_derived following st/mesa state changesBruce Cherniak1-0/+6
Recent change to st/mesa state update logic caused major regressions to swr validation code. swr uses the same validation logic (swr_update_derived) for both draw and Clear calls. New st/mesa state update logic results in certain state objects not being set/bound during Clear. This was causing null ptr exceptions. Creation of static dummy state objects allows setting these pointers during Clear validation, without interfering with relevant state validation. Once fixed, new logic also highlighted an error in dirty bit checking for fragment shader and clip validation. (The alternative is to have a simplified validation routine for Clear. Which may do that at some point.) Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-02-23swr: add fetch shader cacheGeorge Kyriazis1-0/+14
For now, the cache key is all of FETCH_COMPILE_STATE. Use new/delete for swr_vertex_element_state, since we have to call the constructors/destructors of the struct elements. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-01-05swr: remove unneeded llvm version checkTim Rowley1-4/+0
Old test caused breakage with llvm-svn (4.0.0svn), and not needed as the minimum required llvm version for swr is 3.6. Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
2016-11-22swr: color interpolation is also supposed to get perspective divisionIlia Mirkin1-2/+4
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-11-22swr: add sprite coord enable mask to fs keyIlia Mirkin1-1/+2
This fixes gl-coord-replace-doesnt-eliminate-frag-tex-coords Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-11-22swr: rework vert <-> frag shader linkage logicIlia Mirkin1-43/+50
Fixes a few things: - sprite coords only apply to generic varyings, and are a bitmask - back color only applies in 2-sided lighting mode - handle some odd situations between only some front/back colors being there. This is only semi-legal in GL, but we shouldn't start crashing. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-11-22swr: only broadcast color0 value, not all color valuesIlia Mirkin1-1/+2
The way that dual-source blending is described for GLES2 is very odd, and we end up with a shader that both has this property set *and* has a color1 value to be used as the second source. While changing the state tracker is an option, it seems more reliable to verify that the broadcast is only done on color0. Fixes arb_blend_func_extended-fbo-extended-blend-pattern_gles2 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-11-22swr: rework resource layout and surface setupIlia Mirkin1-4/+24
This is a bit of a mega-commit, but unfortunately there's no great way to break this up since a lot of different pieces have to match up. Here we do the following: - change surface layout to match swr's Load/StoreTile expectations - fix sampler settings to respect all sampler view parameters - fix stencil sampling to read from secondary resource - respect pipe surface format, level, and layer settings - fix resource map/unmap based on the new layout logic - fix resource map/unmap to copy proper parts of stencil values in and out of the matching depth texture These fix a massive quantity of piglits, including all the tex-miplevel-selection ones. Note that the swr native miptree layout isn't extremely space-efficient, and we end up using it for all textures, not just the renderable ones. A back-of-the-envelope calculation suggests about 10%-25% increased memory usage for miptrees, depending on the number of LODs. Single-LOD textures should be unaffected. There are a handful of regressions as a result of this change: - Some textureGrad tests, these failures match llvmpipe. (There are debug settings allowing improved gallivm sampling accurancy.) - Some layered clearing tests as swr doesn't currently support that. It was getting lucky before because enough other things were broken. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
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