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path: root/src/gallium/drivers/radeon/radeon_video.c
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2018-11-28winsys/amdgpu: explicitly declare whether buffer_map is permanent or notNicolai Hähnle1-2/+4
Introduce a new driver-private transfer flag RADEON_TRANSFER_TEMPORARY that specifies whether the caller will use buffer_unmap or not. The default behavior is set to permanent maps, because that's what drivers do for Gallium buffer maps. This should eliminate the need for hacks in libdrm. Assertions are added to catch when the buffer_unmap calls don't match the (temporary) buffer_map calls. I did my best to update r600 for consistency (r300 needs no changes because it never calls buffer_unmap), even though the radeon winsys ignores the new flag. As an added bonus, this should actually improve the performance of the normal fast path, because we no longer call into libdrm at all after the first map, and there's one less atomic in the winsys itself (there are now no atomics left in the UNSYNCHRONIZED fast path). Cc: Leo Liu <leo.liu@amd.com> v2: - remove comment about visible VRAM (Marek) - don't rely on amdgpu_bo_cpu_map doing an atomic write Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-09-10radeonsi: merge SI and CI dma_clear_buffer and remove the callbackMarek Olšák1-2/+1
also use assertions for the requirements that offset and size are a multiple of 4. Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-06-19amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbufMarek Olšák1-1/+1
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-27radeonsi: use r600_resource() typecast helperMarek Olšák1-3/+2
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-05radeonsi: remove r600_common_contextMarek Olšák1-5/+5
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05radeonsi: use si_context instead of pipe_context in parameters pt2Marek Olšák1-2/+2
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-04-05radeonsi: use r600_common_context less pt7Marek Olšák1-8/+6
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-11-29radeonsi: remove r600_common_screenMarek Olšák1-3/+3
Most files in gallium/radeon now include si_pipe.h. chip_class and family are now here: sscreen->info.family sscreen->info.chip_class Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29radeonsi: move video queries into si_get.cMarek Olšák1-149/+0
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-17radeon/video: enable encode support for ravenBoyuan Zhang1-1/+2
Enable h.264 encode for vcn hardware (raven) Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2017-11-02radeonsi: remove 'Authors:' commentsMarek Olšák1-6/+0
It's inaccurate. Instead, see the copyright and use "git log" and "git blame" to know the authorship. Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-26radeon/video: add gfx9 offsets when rejoin the video surfaceLeo Liu1-1/+4
For CPU access. Signed-off-by: Leo Liu <leo.liu@amd.com> Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Christian König <christian.koenig@amd.com>
2017-10-07gallium/radeon: remove old r600g code checking chip_class and familyMarek Olšák1-17/+10
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-26r600: fork and import gallium/radeonMarek Olšák1-22/+22
This marks the end of code sharing between r600 and radeonsi. It's getting difficult to work on radeonsi without breaking r600. A lot of functions had to be renamed to prevent linker conflicts. There are also minor cleanups. Acked-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-23radeon/video: Return false explicitly for HEVC if not the caseLeo Liu1-0/+1
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-21radeon/video: MJPEG not support stacked video buffersLeo Liu1-1/+5
So we have to detect it for reallocation of de-interlaced buffers Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21radeon/video: add MJPEG supportLeo Liu1-0/+8
v2: add ASIC and Kernel version check Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2017-07-05gallium/radeon: fix VDPAU breakage, need VRAM with WCMarek Olšák1-1/+2
2017-03-30radeon/uvd: adapt gfx9 surface to uvdLeo Liu1-14/+24
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2017-03-30gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*Marek Olšák1-7/+7
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-13radeon/uvd: enable 10bit HEVC decode v2Christian König1-1/+10
Just use whatever the state tracker allocated. v2: fix msb mode Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-01-05radeonsi: use SDMA in rvid_buffer_clear on CIK-VIMarek Olšák1-2/+2
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26gallium/radeon: stop using PIPE_BIND_CUSTOMMarek Olšák1-1/+1
it has no effect whatsoever Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26gallium/radeon: rename bo_size -> surf_size, bo_alignment -> surf_alignmentMarek Olšák1-2/+2
these names were misleading. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-30radeon/video: don't use sub-allocated buffersNicolai Hähnle1-1/+7
Cc: Christian König <christian.koenig@amd.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97976 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969 Reviewed-by: Christian König <christian.koenig@amd.com>
2016-07-08radeon/uvd: move polaris fw check into radeon_video.c v2Christian König1-3/+13
It's actually not very clever to claim to support H.264 and then fail to create a decoder. v2: prefix FW macro with UVD_. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08radeon/video: fix coding style in radeon_video.c v2Christian König1-15/+15
v2: fix other tabs as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-06-25gallium/radeon: use r600_resource_referenceMarek Olšák1-1/+1
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Vedran Miletić <vedran@miletic.net> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-06-02radeon/uvd: fix the H264 level for Tonga v2Christian König1-1/+1
We support 5.2 for a while now. v2: we even support 5.2 for H264, 5.1 is for HEVC. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: <mesa-stable@lists.freedesktop.org>
2016-05-17Treewide: Remove Elements() macroJan Vesely1-1/+1
Signed-off-by: Jan Vesely <jano.vesely@gmail.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-28radeonsi: rework clear_buffer flagsMarek Olšák1-1/+1
Changes: - don't flush DB for fast color clears - don't flush any caches for initial clears - remove the flag from si_copy_buffer, always assume shader coherency Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-04-27winsys/radeon: remove use_reusable_pool parameter from buffer_createNicolai Hähnle1-1/+1
All callers set this parameter to true. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-27radeon/video: always use the reusable buffer poolNicolai Hähnle1-2/+2
A semantic error was introduced in a past refactoring that caused the bind parameter to be passed into the use_reusable_pool parameter of buffer_create. Since this clearly makes no sense, and there is no clear reason why the cache _shouldn't_ be used, just use the cache always. Cc: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-11radeon/video: enable HEVC main 10 decodeBoyuan Zhang1-2/+6
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-08radeon/uvd: increase max height to 4096 for VI and newerTamil velan1-1/+1
With this issue 'mpv --hwdec=vdpau --vo=vdpau <stream>' fails for vdpau decode if the stream height is 4096. Vdpau decode of height upto 4096 is necessary usecase on amdgpu driver for VI and newer platforms. The fix is in driver specific implementation of "Decoder Query Capabilities" API to return 4096 for VI and newer platforms. With this fix vdpauinfo reports height support as 4096 and mpv for vdpau decode works fine for 4096 height streams. Signed-off-by: Tamil velan <Tamil-Velan.Jayakumar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-08radeon/uvd: disable MPEG1Christian König1-0/+1
The hardware simply doesn't support that correctly. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2015-12-11gallium/radeon: remove radeon_winsys_cs_handleMarek Olšák1-5/+5
"radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf". Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-11-06radeon/uvd: fix VC-1 simple/main profile decode v2Boyuan Zhang1-2/+1
We just needed to set the extra width/height fields to get this working. v2 (chk): rebased, CC stable added, commit message added, fixed coding style Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
2015-10-22radeon/uvd: don't expose HEVC on old UVD hw (v3)Alex Deucher1-32/+18
The section for UVD 2 and older was not updated when HEVC support was added. Reported by Kano on irc. v2: integrate the UVD2 and older checks into the main switch statement. v3: handle encode checking as well. Encode is already checked in the top case statement, so drop encode checks in the lower case statement. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: mesa-stable@lists.freedesktop.org
2015-08-14radeon/uvd: implement HEVC supportBoyuan Zhang1-0/+10
add context buffer to fix H265 uvd decode issue. fix H265 corruption issue caused by incorrect assigned ref_pic_list. v2: disable interlace for HEVC add CZ sps flag workaround fix coding style Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-08-14radeon/video: config encode stacked frame number based on HWLeo Liu1-0/+2
since VCE 3.0 with dual instances, we need stack frames for them. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14radeon/video: add 4K support for decode/encode parametersLeo Liu1-4/+4
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
2015-04-29winsys/radeon: add a private interface for radeon_surfaceMarek Olšák1-1/+1
2015-04-29winsys/radeon: move radeon_winsys.h to drivers/radeonMarek Olšák1-1/+0
2015-01-07radeonsi: only flush the right set of caches for CP DMA operationsMarek Olšák1-1/+2
That's either framebuffer caches or caches for shader resources. The motivation is that framebuffer caches need to be flushed very rarely here. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11radeon/video: use the hw to initial clear the buffersChristian König1-6/+4
Less CPU overhead and avoids contention over CPU accessible memory on startup. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11radeon/video: use more of the common buffer code v2Christian König1-30/+23
In preparation to using buffers clears with the hw engine(s). v2: split out flipping to using hw buffer clears. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-28gallium/radeon: cleanup header inclusionEmil Velikov1-1/+1
- Add top_srcdir/src/gallium/winsys to GALLIUM_DRIVER_C{XXFLAGS}. - Remove top_srcdir/src/gallium/drivers/radeon from the includes. As a result: - Common radeon headers are prefixed with 'radeon/' - Winsys header inclusion is prefixed 'radeon/drm' Cc: Marek Olšák <marek.olsak@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-27radeon/uvd: remove comment about RV770Alex Deucher1-1/+0
It doesn't seem to support field based decode after testing. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2014-08-26radeon/uvd: fix field handling on R6XX style UVDChristian König1-2/+5
The first UVD generation can only do frame based output. Signed-off-by: Christian König <christian.koenig@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-13 23:32:43 +0000