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path: root/src/gallium/drivers/radeon/r600_texture.c
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2014-06-03r600g,radeonsi: disable fast clear if render condition is onMarek Olšák1-0/+3
For some reason, CP DMA doesn't follow the predicate bit if I enable it, so this is the only option. This fixes piglit: spec/NV_conditional_render/clear Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-04-25r600g: fix for HTILE on R6xxMarek Olšák1-0/+6
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-04-25r600g: fix MSAA resolve on R6xx when the destination is 1D-tiledMarek Olšák1-0/+6
Cc: 10.0 10.1 mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-04-16r600g/radeonsi: Map transfer staging texture unsynchronized when possibleMichel Dänzer1-0/+2
The transfer staging texture is always freshly allocated, so for write-only transfers we don't need to explicitly wait for the BO to become idle. Squeezes a few hundered MB/s more out of x11perf -shmput500 with glamor. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-04-15r600g/radeonsi: Use caching buffer manager for textures as wellMichel Dänzer1-1/+1
Significantly reduces BO allocation / destruction overhead for transfers, e.g. measurable via x11perf -shm{ge,pu}t* with glamor. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-04-09radeonsi: allow fast color clear and Hyper-Z with 1D-tiled surfaces on CIKMarek Olšák1-5/+5
This depends on my kernel fix. Hyper-Z is still disabled by default.
2014-04-09r600g,radeonsi: set correct initial domain for shared resourcesMarek Olšák1-1/+1
2014-04-04Revert "radeon: just don't map VRAM buffers at all"Leo Liu1-2/+2
This reverts commit 96e8b916a7a39a9ba58e92d1ad77b5501de63ac7. In the case of VCE encoding with raw YUV file, CPU load directly to VRAM is faster than combination of CPU writing to GTT and then blit to VRAM with GPU. Reviewed-by: Christian König <christian.koenig@amd.com>
2014-03-22radeonsi: disable fast color clear for 1D-tiled surfaces on CIKMarek Olšák1-0/+6
This will be re-enabled once my kernel fix lands.
2014-03-11r600g,radeonsi: use a fallback in dma_copy instead of failingMarek Olšák1-13/+5
v2: - allow byte-aligned DMA buffer copies on Evergreen - fix piglit/texsubimage regression - use the fallback for 3D copies (depth > 1) as well
2014-03-11radeonsi: implement fast color clearMarek Olšák1-1/+5
This works for both multi-sample and single-sample color buffers. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-03-11r600g: move fast color clear code to a common placeMarek Olšák1-2/+81
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-03-11r600g,radeonsi: move CMASK register values from r600_surface to r600_textureMarek Olšák1-2/+25
When doing fast clear for single-sample color buffers for the first time, a CMASK buffer has to be allocated and the CMASK state in all pipe_surfaces referencing the color buffer must be updated. Updating all surfaces is kinda silly, so let's move the values to r600_texture instead. This is only for Evergreen and later. R600-R700 don't have fast clear. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-03-04radeonsi: move translate_colorswap to common codeMarek Olšák1-0/+54
Also translate the Y__X swizzle. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-25r600g,radeonsi: consolidate create_surface and surface_destroyMarek Olšák1-1/+51
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-02-13radeon: reverse DBG_NO_HYPERZ logicAlex Deucher1-1/+1
Change the flag to DBG_HYPERZ and reverse the logic so setting the flag enabled the feature. This disables hyperz on r600g and radeonsi by default. It can be enabled by setting the env var. There are just too many issues with certain apps so leave it disabled for now until we sort out the issues with the problematic apps. Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=58660 https://bugs.freedesktop.org/show_bug.cgi?id=64471 https://bugs.freedesktop.org/show_bug.cgi?id=66352 https://bugs.freedesktop.org/show_bug.cgi?id=68799 https://bugs.freedesktop.org/show_bug.cgi?id=72685 https://bugs.freedesktop.org/show_bug.cgi?id=73088 https://bugs.freedesktop.org/show_bug.cgi?id=74428 https://bugs.freedesktop.org/show_bug.cgi?id=74803 https://bugs.freedesktop.org/show_bug.cgi?id=74863 https://bugs.freedesktop.org/show_bug.cgi?id=74892 https://bugzilla.kernel.org/show_bug.cgi?id=70411 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: "10.1" "10.0" <mesa-stable@lists.freedesktop.org> Acked-by: Marek Olšák <marek.olsak@amd.com>
2014-02-06gallium: remove PIPE_USAGE_STATICMarek Olšák1-4/+4
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-02-06r600g,radeonsi: set resource domains in one place (v2)Marek Olšák1-5/+2
v2: This doesn't change the behavior. It only moves the tiling check to r600_init_resource and removes the usage parameter. Reviewed-by: Christian König <christian.koenig@amd.com>
2014-02-06radeon: just don't map VRAM buffers at allChristian König1-2/+2
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-28r600g,radeonsi: consolidate the contents of r600_resource.cMarek Olšák1-6/+12
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-01-06radeonsi: disable HTILE for 1D-tiled depth-stencil buffersMarek Olšák1-0/+5
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12radeon: Allocate htile buffer for SI in r600_texture.Andreas Hartmetz1-15/+67
2013-12-12radeon: rearrange r600_texture and related code a bit.Andreas Hartmetz1-29/+29
This should make the differences and similarities between color and depth buffer handling more clear.
2013-12-12winsys/radeon: set/get the scanout flag with the tiling ioctlsMarek Olšák1-4/+5
If we assume that all buffers allocated by the DDX are scanout, a new flag that says "this is not scanout" has to be added to support the non-scanout buffers and maintain backward compatibility. This fixes bad rendering on Wayland. The flag is defined as: #define RADEON_TILING_R600_NO_SCANOUT RADEON_TILING_SWAP_16BIT AFAIK, RADEON_TILING_SWAP_16BIT is not used on SI. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-03gallium/radeon: use PRIu64 macro for printing uint64_tEmil Velikov1-3/+4
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2013-11-23radeonsi: implement MSAA for CIKMarek Olšák1-3/+7
There are also some changes to the printfs. Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2013-11-23radeonsi: enable 2D tiling on CIKMarek Olšák1-4/+0
libdrm does the DRM version check and decides if 2D tiling is used. Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2013-10-13radeon: use staging for mapping linear texturesGrigori Goronzy1-0/+6
Textures that likely reside in VRAM, are mapped for reading and don't require direct mapping should be staged into GTT, to avoid bad performance. This fixes readback performance of VDPAU surfaces. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-10-03r600g: fix ínitialization of non_disp_tiling flagMarek Olšák1-4/+5
This fixes a regression caused by e64633e8c3a5498998a45ab721bf80edca101cf5
2013-09-29radeon: make texture logging more usefulMarek Olšák1-17/+16
This has been very useful for tracking down bugs in libdrm. The *_PRINT_TEXDEPTH environment variables were probably never used, so I removed them.
2013-09-29r600g,radeonsi: share r600_texture.cMarek Olšák1-0/+1015
The function r600_choose_tiling is new and needs a review. The only change in functionality is that it enables 2D tiling for compressed textures on SI. It was probably accidentally turned off. v2: don't make scanout buffers linear
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