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2019-12-10freedreno/a5xx+a6xx: split LRZ layout to per-genRob Clark1-0/+31
Seems to be a bit different for a6xx, so let's split this out. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-06freedreno: reorder format checkFritz Koenig1-2/+2
With the addition of the planar formats helper, the planar formats no longer have a valid block.bits field. Calling util_format_get_blocksize therefore asserts. Reorder the check to see if the format is supported before doing the query to get the blocksize. Fixes: 20f132e5eff2d ("gallium/util: add planar format layouts and helpers") Signed-off-by: Fritz Koenig <frkoenig@google.com> Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-11-26freedreno: switch to layout helperRob Clark6-39/+39
The slices table and most of the other layout fields in the freedreno_resource moves into fdl_layout. v2: Changes by anholt to not have duplicate fields, which was introducing a surprising behavior change in resource layout (using the level_linear helper before the setup of the shadowed fields) Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26freedreno: Convert the slice struct to the new resource header.Eric Anholt5-9/+9
This gets the worst of the sed required for shared resource layout out of the way. The texture layout comment is dropped now that we're referencing the shared header, which has a more complete description. Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26freedreno: Introduce a fd_resource_tile_mode() helper.Eric Anholt3-10/+5
Multiple places were doing the same thing to get the tile mode of a level, so refactor it out. This will make the shared resource helper transition cleaner. Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26freedreno: use rsc->slice accessor everywhereRob Clark3-7/+10
This will make it easier to extract the slice table out into a layout helper. Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-21freedreno/perfcntrs: add accessor to get per-gen tablesRob Clark1-8/+0
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21freedreno/perfcntrs: move to shared locationRob Clark1-739/+0
This should eventually be useful for VK_KHR_performance_query as well. And in the more near term, for fdperf. Attempt to not break android build is best-effort and untested. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21freedreno/perfcntrs: remove gallium dependenciesRob Clark1-1/+3
Prep work to move to a shared location. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21freedreno/perfcntrs: small cleanupRob Clark1-30/+1
When we had one gen supporting performance counters, it made sense to have these builder macros in the .c file with the table. But time has come to de-duplicate. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-14util: Move gallium's PIPE_FORMAT utils to /util/format/Eric Anholt6-6/+6
To make PIPE_FORMATs usable from non-gallium parts of Mesa, I want to move their helpers out of gallium. Since u_format used util_copy_rect(), I moved that in there, too. I've put it in a separate directory in util/ because it's a big chunk of related code, and it's not clear to me whether we might want it as a separate library from libmesa_util at some point. Closes: #1905 Acked-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-09-25freedreno: Rename vp and fp to vs and fs in fd_program_stateobjKristian H. Kristensen2-13/+13
We're using vs and fs now, and adding hs, ds and gs soon. It's confusing enough that we have both DS/TCS and HS/TES. At least for VS and FS there doesn't have to be multiple names. Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-09-18freedreno/a6xx: Share shader state constructor and destructorKristian H. Kristensen1-43/+1
Also, swap vs and fs constructor or so fs comes first. Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06freedreno/a6xx: Implement primitive count queries on GPUKristian H. Kristensen1-1/+1
The driver can't determine PIPE_QUERY_PRIMITIVES_GENERATED or PIPE_QUERY_PRIMITIVES_EMITTED once we support geometry or tessellation, since these stages add primitives at runtime. Use the WRITE_PRIMITIVE_COUNTS event to write back the primitive counts and implement a hw query for this. Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-09-03freedreno: Fix the type of single-component scaled vertex attrs.Eric Anholt1-3/+3
This looks like clear copy-and-pasteos, and fixes: dEQP-GLES2.functional.draw.random.40 (on A307 and A630, both tested in the new CI farm) Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-08-13freedreno/all: move more emit helpers to screenRob Clark1-3/+2
framebuffer_barrier() still depends on the ctx, but the rest can move to screen. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-08-13freedreno/a3xx-a6xx+ir3: move emit_const* to screenRob Clark1-2/+3
These don't need to be in context, and we'll need them in screen in a later patch. Plus it's a good cleanup. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-08-13freedreno/a5xx: add fd5_emit_init_screen()Rob Clark3-0/+9
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-08-13freedreno/a5xx: call fd5_emit_ib() directly from fd5Rob Clark3-16/+16
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-07-22gallium: switch boolean -> bool at the interface definitionsIlia Mirkin1-2/+2
This is a relatively minimal change to adjust all the gallium interfaces to use bool instead of boolean. I tried to avoid making unrelated changes inside of drivers to flip boolean -> bool to reduce the risk of regressions (the compiler will much more easily allow "dirty" values inside a char-based boolean than a C99 _Bool). This has been build-tested on amd64 with: Gallium drivers: nouveau r300 r600 radeonsi freedreno swrast etnaviv v3d vc4 i915 svga virgl swr panfrost iris lima kmsro Gallium st: mesa xa xvmc xvmc vdpau va Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26freedreno: drop unused arg from fd_batch_flush()Rob Clark1-1/+1
The `force` arg has been unused for a while.. but apparently I forgot to garbage collect it. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-24freedreno/a5xx: fix batch leak in fd5 blitter pathRob Clark1-0/+1
Fixes: 3d198926a48 freedreno: use fd_bc_alloc_batch instead of fd_batch_create. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-12freedreno: use util_dynarray_clear instead of util_dynarray_resize(_, 0)Nicolai Hähnle1-1/+1
This is more expressive and simplifies a subsequent change. v2: - fix one more call-site after rebase Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-06-11freedreno/a5xx: enable a540Rob Clark1-2/+13
Tested-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-11freedreno/a5xx: Fix indirect draw max_indices calculationEduardo Lima Mitev1-2/+1
The number of elements to draw should not be affected by the offset. A similar fix was submitted for a6xx at 79180a05. Fixes these dEQP tests on a5xx: dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_separate_grid_500x500_drawcount_8 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_separate_grid_500x500_drawcount_2500 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawarrays_separate_grid_500x500_drawcount_2500 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawarrays_combined_grid_500x500_drawcount_2500 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_combined_grid_500x500_drawcount_8 dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_combined_grid_500x500_drawcount_2500 Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-06-03freedreno/ir3: fix counting and printing for half registers.Hyunjun Ko1-1/+1
v2: defining 0x100 and use this for setting the FS_OUTPUT_REG.HALF_PRECISION Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-03freedreno/ir3: Use output type size to set OUTPUT_REG_HALF_PRECISIONNeil Roberts1-2/+1
Previously the A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION was set depending on whether half_precision was set in the shader key. With support for mediump precision, it is possible to have different outputs use different precisions. That means we can’t have a global shader state to specify it. Instead it now tries to copy the half-float-ness from the nir_variable for the output into the ir3_shader_variant. This is then used to decide whether to set half-precision for each output. The a6xx version is copied from the a5xx code but it has not been tested. v2. [Hyunjun Ko (zzoon@igalia.com)] There's the half flag recently added, which represents precision based on IR3_REG_HALF. Now use this flag to avoid duplication. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-16freedreno: Fix assertion failures in context setup in shader-db mode.Eric Anholt1-0/+1
The TTN path needs access to the screen to make the right decisions about lowering, but we didn't have pctx->screen set up at fdN_prog_init time. Reviewed-by: Rob Clark <robdclark@gmail.com> Tested-by: Eduardo Lima Mitev <elima@igalia.com>
2019-05-13freedreno: Silence compiler warnings about uninit 'layers'Eric Anholt1-1/+1
My gcc can't see that the uninitialized value from the PIPE_BUFFER case isn't used from the !PIPE_BUFFER cases later. Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-04-25compiler: rename SYSTEM_VALUE_VARYING_COORDRob Clark1-1/+1
And add corresponding enums for different sorts of varying interpolation. Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-03-22freedreno/ir3: rename has_kill to no_earlyzRob Clark2-2/+2
There are other cases where we need to disable early-z, like image writes. So rename to something more generic. Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-05freedreno: Plumb pipe_screen through to irX_tgsi_to_nir.Timur Kristóf2-2/+2
This patch makes it possible for freedreno to pass a pipe_screen to tgsi_to_nir. This will be needed when tgsi_to_nir supports reading pipe capabilities. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Tested-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-02-16freedreno/ir3: add image/ssbo <-> ibo/tex mappingRob Clark3-67/+32
Images and SSBOs don't map directly to the hw. They end up being part texture and part something else. Starting with a6xx, the hack used for a5xx to smash the image tex state into hw texture state starting from MAX counting down won't work, because we start using tex state also for SSBO read. Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-29freedreno/a5xx: fix blitter nr_samples checkRob Clark1-1/+2
nr_samples for non-MSAA case could be either zero or one. Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-08freedreno: Move register constant files to src/freedreno.Bas Nieuwenhuizen1-5226/+0
This way they can be shared. Build tested with meson, but not too sure on the autotools stuff though. Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Acked-by: Rob Clark <robdclark@gmail.com>
2019-01-03freedreno: rework blit APIRob Clark2-4/+5
First step to unify the way fd5 and fd6 blitter works. Currently a6xx bypasses the blit API in order to also accelerate resource_copy_region() But this approach can lead to infinite recursion: #0 fd_alloc_staging (ctx=0x5555936480, rsc=0x7fac485f90, level=0, box=0x7fbab29220) at ../src/gallium/drivers/freedreno/freedreno_resource.c:291 #1 0x0000007fbdebed04 in fd_resource_transfer_map (pctx=0x5555936480, prsc=0x7fac485f90, level=0, usage=258, box=0x7fbab29220, pptrans=0x7fbab29240) at ../src/gallium/drivers/freedreno/freedreno_resource.c:479 #2 0x0000007fbe5c5068 in u_transfer_helper_transfer_map (pctx=0x5555936480, prsc=0x7fac485f90, level=0, usage=258, box=0x7fbab29220, pptrans=0x7fbab29240) at ../src/gallium/auxiliary/util/u_transfer_helper.c:243 #3 0x0000007fbde2dcb8 in util_resource_copy_region (pipe=0x5555936480, dst=0x7fac485f90, dst_level=0, dst_x=0, dst_y=0, dst_z=0, src=0x7fac47c780, src_level=0, src_box_in=0x7fbab2945c) at ../src/gallium/auxiliary/util/u_surface.c:350 #4 0x0000007fbdf2282c in fd_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47c780, src_level=0, src_box=0x7fbab2945c) at ../src/gallium/drivers/freedreno/freedreno_blitter.c:173 #5 0x0000007fbdf085d4 in fd6_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47c780, src_level=0, src_box=0x7fbab2945c) at ../src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:587 #6 0x0000007fbde2f3d0 in util_try_blit_via_copy_region (ctx=0x5555936480, blit=0x7fbab29430) at ../src/gallium/auxiliary/util/u_surface.c:864 #7 0x0000007fbdec02c4 in fd_blit (pctx=0x5555936480, blit_info=0x7fbab29588) at ../src/gallium/drivers/freedreno/freedreno_resource.c:993 #8 0x0000007fbdf08408 in fd6_blit (pctx=0x5555936480, info=0x7fbab29588) at ../src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:546 #9 0x0000007fbdebdc74 in do_blit (ctx=0x5555936480, blit=0x7fbab29588, fallback=false) at ../src/gallium/drivers/freedreno/freedreno_resource.c:129 #10 0x0000007fbdebe58c in fd_blit_from_staging (ctx=0x5555936480, trans=0x7fac47b7e8) at ../src/gallium/drivers/freedreno/freedreno_resource.c:326 #11 0x0000007fbdebea38 in fd_resource_transfer_unmap (pctx=0x5555936480, ptrans=0x7fac47b7e8) at ../src/gallium/drivers/freedreno/freedreno_resource.c:416 #12 0x0000007fbe5c5c68 in u_transfer_helper_transfer_unmap (pctx=0x5555936480, ptrans=0x7fac47b7e8) at ../src/gallium/auxiliary/util/u_transfer_helper.c:516 #13 0x0000007fbde2de24 in util_resource_copy_region (pipe=0x5555936480, dst=0x7fac485f90, dst_level=0, dst_x=0, dst_y=0, dst_z=0, src=0x7fac47b8e0, src_level=0, src_box_in=0x7fbab2997c) at ../src/gallium/auxiliary/util/u_surface.c:376 #14 0x0000007fbdf2282c in fd_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47b8e0, src_level=0, src_box=0x7fbab2997c) at ../src/gallium/drivers/freedreno/freedreno_blitter.c:173 #15 0x0000007fbdf085d4 in fd6_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47b8e0, src_level=0, src_box=0x7fbab2997c) at ../src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:587 ... Instead rework the API to push the fallback back to core code, so that we can rework resource_copy_region() to have it's own fallback path, and then finally convert fd6 over to work in the same way. This also makes ctx->blit() optional, and cleans up some unnecessary callers. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-22freedreno: update generated headersRob Clark1-3/+3
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-13freedreno: update generated headersRob Clark1-4/+4
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-13freedreno: also set DUMP flag on shadersRob Clark1-1/+1
If we emit shader as a pointer to a GEM object, also set the RELOC_DUMP flag as a hint to kernel that this is a useful buffer to snapshot for debug dumps. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-13freedreno: debug GEM obj namesRob Clark2-3/+3
With a recent enough kernel, set debug names for GEM BOs, which will show up in $debugfs/gem Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-07freedreno/ir3: track max flow control depth for a5xx/a6xxRob Clark1-2/+2
Rather than just hard-coding BRANCHSTACK size. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-07freedreno: update generated headersRob Clark1-5/+5
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-07freedreno/a5xx+a6xx: remove unused fs/vs pvt memRob Clark2-10/+0
copy/pasta from older gens Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27freedreno: update generated headersRob Clark1-5/+5
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27freedreno: move ir3 to common locationRob Clark3-3/+4
Move (most of) the ir3 compiler to src/freedreno/ir3 so that it can be re-used by some future vulkan driver. The parts that are gallium specific have been refactored out and remain in the gallium driver. Getting the move done now so that it can happen before further refactoring to support a6xx specific instructions. NOTE also removes ir3_cmdline compiler tool from autotools build since that was easier than fixing it and I normally use meson build. Waiting patiently for the day that we can remove *everything* from the autotools build. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27freedreno/ir3: split up ir3_shaderRob Clark1-1/+1
Split the parts that are gallium specific into ir3_gallium so the rest can move to a common location outside of gallium. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27freedreno/ir3: remove pipe_stream_output_info dependencyRob Clark2-5/+5
A bit annoying to have to copy into our own struct. But this is something the compiler really needs to know, at least on earlier generations where streamout is implemented in shader. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27freedreno: shader_t -> gl_shader_stageRob Clark2-5/+5
Just massive search/replace for the most part. Step towards removing ir3 dependency on disasm.h which is shared by a2xx. One step closer to being able to move ir3 out of gallium. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-06freedreno: update generated headersRob Clark1-3/+3
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-26freedreno: import libdrm_freedreno + redesign submitRob Clark2-4/+1
In the pursuit of lowering driver overhead, it became clear that some amount of redesign of how libdrm_freedreno constructs the submit ioctl would be needed. In particular, as the gallium driver is starting to make heavier use of CP_SET_DRAW_STATE state groups/objects, the over- head of tracking cmd buffers and relocs becomes too much. And for "streaming" state, which isn't ever reused (like uniform uploads) the overhead of allocating/freeing ringbuffer[1] objects is too high. This redesign makes two main changes: 1) Introduces a fd_submit object for tracking bos and cmds table for the submit ioctl, making ringbuffer objects more light- weight. This was previously done in the ringbuffer. But we have many ringbuffer instances involved in a submit (gmem + draw + potentially 1000's of state-group rbs), and only need a single bos and cmds table. (Reloc table is still per-rb) The submit is also a convenient place for a slab allocator for ringbuffer objects. Other options would have required locking because, while we can guarantee allocations will only happen on a single thread, free's could happen either on the application thread or the flush_queue thread. With the slab allocator in the submit object, any frees that happen on the flush_queue thread happen after we know that the application thread is done with the submit. 2) Introduce a new "softpin" msm_ringbuffer_sp implementation that does not use relocs and only has cmds table entries for IB1 (ie. the cmdstream buffers that kernel needs to CP_INDIRECT_BUFFER to from the RB). To do this properly will require some updates on the kernel side, so whether you get the softpin or legacy submit/ringbuffer implementation at runtime depends on your kernel version. To make all these changes in libdrm would basically require adding a libdrm_freedreno2, so this is a good point to just pull the libdrm code into mesa. Plus it allows for using mesa's hashtable, slab allocator, etc. And it lets us have asserts enabled for debug mesa buids but omitted for release builds. And it makes life easier if further API changes become necessary. At this point I haven't tried to pull in the kgsl backend. Although I left the level of vfunc indirection which would make it possible to have other backends. (And this was convenient to keep to allow for the "softpin" ringbuffer to coexist.) NOTE: if bisecting a build error takes you here, try a clean build. There are a bunch of ways things can go wrong if you still have libdrm_freedreno cflags. [1] "ringbuffer" is probably a bad name, the only level of cmdstream buffer that is actually a ring is RB managed by kernel. User- space cmdstream is all IB1/IB2 and state-groups. Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-17 04:07:43 +0000