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2013-10-13i965: Add the family name to the PCI ID table.Kenneth Graunke2-94/+94
I removed this a while ago, since we never used it, but I'm finally resurrecting the idea in the next commits. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-13i965: Remove #define name from PCI ID table.Kenneth Graunke2-94/+94
Nothing uses the #define name, and it's not terribly useful - the numerical ID serves the same purpose. The only thing we could really do with it is generate slightly prettier preprocessed code. But who looks at that? Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-09-06radeonsi: add berlin pci idsAlex Deucher1-0/+22
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeonsi: add kabini pci idsAlex Deucher1-0/+17
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeonsi: add bonaire pci idsAlex Deucher1-0/+9
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-06intel: Use the CHIPSET macro in the PCI ID tables for the device name.Kenneth Graunke3-110/+110
Putting the human readable device names directly in the PCI ID list consolidates things in one place. It also makes it easy to customize the name on a per-PCI ID basis without a huge code explosion. Based on a patch by Kristian Høgsberg. v2: Fix 830M/845G names and #undef CHIPSET (caught by Emit Velikov). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-06-06intel: Remove 'misc' parameter from CHIPSET macro in PCI ID tables.Kenneth Graunke3-110/+110
This has never actually been used for anything. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-06-05i965: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi1-0/+24
At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. NOTE: This is a candidate for stable branches. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-14radeonsi: add Hainan pci idsAlex Deucher1-0/+7
Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-05-09i965: make GT3 machines work as GT3 instead of GT2Paulo Zanoni1-12/+12
We were not allowed to say the "GT3" name, but we really needed to have the PCI IDs because too many people had such machines, so we had to make the GT3 machines work as GT2. Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :) NOTE: This is a candidate for stable branches. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-25radeonsi: add new SI pci idsAlex Deucher1-0/+3
Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-25r600g: add new richland pci idsAlex Deucher1-0/+2
Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-16i965: Enable the Bay Trail platform.Kenneth Graunke1-0/+5
This patch adds PCI IDs for Bay Trail (sometimes called Valley View). As far as the 3D driver is concerned, it's very similar to Ivybridge, so the existing code should work just fine. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-15r600g: add Richland APU pci idsAlex Deucher1-0/+11
Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-03-03i965: Fix Crystal Well PCI IDs.Kenneth Graunke1-9/+9
The second digit was off by one, which meant we accidentally treated GTn as GT(n-1). This also meant no support for GT1 at all. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-04radeonsi: add Oland pci idsAlex Deucher1-0/+14
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Note: this is a candidate for the 9.1 branch.
2012-11-21radeonsi: add a new SI pci idAlex Deucher1-0/+1
Note: this is a candidate for the stable branch. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-16radeonsi: add some new SI pci idsAlex Deucher1-0/+3
Note: this is a candidate for the stable branch. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-07i965: add more Haswell PCI IDsPaulo Zanoni1-1/+32
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-06radeonsi: add some new pci idsAlex Deucher1-0/+3
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-06r600g: add additional evergreen pci idsAlex Deucher1-0/+3
Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-05r600g: add new Trinity PCI idsAlex Deucher1-0/+17
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-05r600g: add new Sumo, Palm, BTC pci idsAlex Deucher1-0/+5
Note this is a candidate for the stable branch. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-05radeonsi: add new SI pci idsAlex Deucher1-5/+6
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-04-13radeonsi: initial WIP SI codeTom Stellard2-0/+47
This commit adds initial support for acceleration on SI chips. egltri is starting to work. The SI/R600 llvm backend is currently included in mesa but that may change in the future. The plan is to write a single gallium driver and use gallium to support X acceleration. This commit contains patches from: Tom Stellard <thomas.stellard@amd.com> Michel Dänzer <michel.daenzer@amd.com> Alex Deucher <alexander.deucher@amd.com> Vadim Girlin <vadimgirlin@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> The following commits were squashed in: ====================================================================== radeonsi: Remove unused winsys pointer This was removed from r600g in commit: commit 96d882939d612fcc8332f107befec470ed4359de Author: Marek Olšák <maraeo@gmail.com> Date: Fri Feb 17 01:49:49 2012 +0100 gallium: remove unused winsys pointers in pipe_screen and pipe_context A winsys is already a private object of a driver. ====================================================================== radeonsi: Copy color clamping CAPs from r600 Not sure if the values of these CAPS are correct for radeonsi, but the same changed were made to r600g in commit: commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc Author: Marek Olšák <maraeo@gmail.com> Date: Mon Jan 23 03:11:17 2012 +0100 st/mesa: do vertex and fragment color clamping in shaders For ARB_color_buffer_float. Most hardware can't do it and st/mesa is the perfect place for a fallback. The exceptions are: - r500 (vertex clamp only) - nv50 (both) - nvc0 (both) - softpipe (both) We also have to take into account that r300 can do CLAMPED vertex colors only, while r600 can do UNCLAMPED vertex colors only. The difference can be expressed with the two new CAPs. ====================================================================== radeonsi: Remove PIPE_CAP_OUTPUT_READ This CAP was dropped in commit: commit 04e324008759282728a95a1394bac2c4c2a1a3f9 Author: Marek Olšák <maraeo@gmail.com> Date: Thu Feb 23 23:44:36 2012 +0100 gallium: remove PIPE_SHADER_CAP_OUTPUT_READ r600g is the only driver which has made use of it. The reason the CAP was added was to fix some piglit tests when the GLSL pass lower_output_reads didn't exist. However, not removing output reads breaks the fallback for glClampColorARB, which assumes outputs are not readable. The fix would be non-trivial and my personal preference is to remove the CAP, considering that reading outputs is uncommon and that we can now use lower_output_reads to fix the issue that the CAP was supposed to workaround in the first place. ====================================================================== radeonsi: Add missing parameters to rws->buffer_get_tiling() call This was changed in commit: commit c0c979eebc076b95cc8d18a013ce2968fe6311ad Author: Jerome Glisse <jglisse@redhat.com> Date: Mon Jan 30 17:22:13 2012 -0500 r600g: add support for common surface allocator for tiling v13 Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height < 64. Fix r300g. v12 Fix linear case when pitch*height < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <jglisse@redhat.com> ====================================================================== radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY This was removed in commit: commit 62f44f670bb0162e89fd4786af877f8da9ff607c Author: Marek Olšák <maraeo@gmail.com> Date: Mon Mar 5 13:45:00 2012 +0100 Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY" This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc. It was decided to refactor the transfer API instead of adding workarounds to address the performance issues. ====================================================================== radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT. Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90. ====================================================================== radeonsi: nuke the fallback for vertex and fragment color clamping Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853. ====================================================================== radeonsi: don't expose transform_feedback2 without kernel support Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48. ====================================================================== radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL. Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f. ====================================================================== radeonsi: set minimum point size to 1.0 for non-sprite non-aa points. Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc. ====================================================================== radeonsi: rework and consolidate stencilref state setting. Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070. ====================================================================== radeonsi: cleanup setting DB_SHADER_CONTROL. Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b. ====================================================================== radeonsi: Get rid of register masks. Ported from r600g commits 3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2. ====================================================================== radeonsi: get rid of r600_context_reg. Ported from r600g commits 9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f. ====================================================================== radeonsi: Fix regression from 'Get rid of register masks'. ====================================================================== radeonsi: optimize r600_resource_va. Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174. ====================================================================== radeonsi: remove u8,u16,u32,u64 types. Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5. ====================================================================== radeonsi: merge r600_context with r600_pipe_context. Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0. ====================================================================== radeonsi: Miscellaneous context cleanups. Ported from r600g commits e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888. ====================================================================== radeonsi: add a new simple API for state emission. Ported from r600g commits 621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e. ====================================================================== radeonsi: Also remove sbu_flags member of struct r600_reg. Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions, so some code needs to be disabled for now. ====================================================================== radeonsi: Miscellaneous simplifications. Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and b0337b679ad4c2feae59215104cfa60b58a619d5. ====================================================================== radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION. Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a. ====================================================================== radeonsi: Use a fake reloc to sleep for fences. Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4. ====================================================================== radeonsi: adapt to get_query_result interface change. Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.
2012-04-01intel: add PCI IDs for Ivy Bridge GT2 server variantEugeni Dodonov1-0/+1
Those IDs are used by Bromolow. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-03-30intel: Add some PCI IDs for Haswell.Kenneth Graunke1-0/+5
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-03-20r600g: add support for TN (trinity) APUsAlex Deucher1-0/+8
Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2011-12-12r600g: add some new pci idsAlex Deucher1-0/+10
fixes: https://bugs.freedesktop.org/show_bug.cgi?id=43739 Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2011-12-01r600g: add some new pci idsAlex Deucher1-0/+8
Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2011-11-14radeon: add some missing FireMV pci idsAlex Deucher2-0/+3
Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2011-11-07radeon: cleanup radeon shared code after r300 and r600 classic drivers removalFabio Pedretti1-2/+0
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-08-27pci_ids: add vmwgfx pci id listChia-I Wu2-0/+8
There is only one chipset 15ad:0405 VMware SVGA II Adapter
2011-08-26dri: Remove all DRI1 driversIan Romanick1-11/+0
Acked-by: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Marek Olšák <maraeo@gmail.com> Acked-by: Alan Coopersmith <alan.coopersmith@oracle.com> Acked-by: Jakob Bornecrantz <jakob@vmware.com> Acked-by: Dave Airlie <airlied@redhat.com> Build-Tested-by: Jakob Bornecrantz <jakob@vmware.com> Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2011-07-15r600c/g: add new NI pci idsAlex Deucher1-0/+2
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2011-06-07r300_pci_ids: set families to match r300gMarek Olšák1-42/+49
2011-06-07r300_pci_ids: add missing 4B48Marek Olšák1-0/+1
Found in r300_chipset.h.
2011-06-07egl_dri2: Use external driver pci listBenjamin Franzke1-0/+77
Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
2011-06-07Add radeon pci id listsBenjamin Franzke4-0/+526
Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
2011-06-07Add intel pci id listsBenjamin Franzke3-0/+46
Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-18 03:19:50 +0000