summaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
7 daysiris/gfx12.5: Pass non-empty push constant data to PS stage for TBIMR workaro...Francisco Jerez2-4/+51
7 daysanv/gfx12.5: Pass non-empty push constant data to PS stage for TBIMR workaround.Francisco Jerez3-5/+48
7 daysintel/brw: Implement null push constant workaround.Francisco Jerez2-1/+5
2024-06-21anv/xe2+: Fix format of scratch space surface address in various 3DSTATE pack...Francisco Jerez3-3/+16
2024-06-21iris/xe2+: Fix format of scratch space surface address in various 3DSTATE pac...Francisco Jerez1-4/+17
2024-05-14intel/isl: Update quote for XeHP's CCS halign ruleNanley Chery1-1/+1
2024-05-14intel/isl: Reduce halign for disabled CCS on XeHPNanley Chery1-7/+25
2024-04-01intel/brw/xehp+: Drop redundant arguments of lsc_msg_desc*().Francisco Jerez4-94/+44
2024-04-01intel/eu/xehp+: Don't initialize mlen and rlen descriptor fields from lsc_msg...Francisco Jerez1-11/+0
2024-04-01intel/brw/xehp+: Replace lsc_msg_desc_dest_len()/lsc_msg_desc_src0_len() with...Francisco Jerez5-41/+77
2024-03-01intel/brw: Allow CSE on TXF_CMS_W_GFX12_LOGICALKenneth Graunke1-0/+1
2023-11-01iris: handle tile case where cso width, height is zeroTapani Pälli1-0/+3
2023-10-30anv: Add more space for init_render_queue_state() batch (MTL regression)Jordan Justen1-1/+1
2023-10-27intel/xehp: Enable TBIMR by default.Francisco Jerez2-2/+2
2023-10-27intel/xehp+: Use TBIMR tile box check in order to avoid performance regressions.Francisco Jerez3-0/+4
2023-10-27intel/xehp+: Adjust TBIMR batch size based on slice count.Francisco Jerez4-0/+21
2023-10-27intel/xehp: Adjust TBIMR performance chicken bits.Francisco Jerez3-0/+24
2023-10-27anv/xehp+: Enable TBIMR in generated draw calls.Francisco Jerez4-1/+10
2023-10-27anv/xehp: Implement TBIMR tile pass setup and pipeline bandwidth estimation.Francisco Jerez3-0/+183
2023-10-27iris/xehp: Implement TBIMR tile pass setup and pipeline bandwidth estimation.Francisco Jerez1-0/+93
2023-10-27intel/xehp+: Define driconf option for selectively disabling TBIMR.Francisco Jerez8-0/+12
2023-10-27intel/xehp+: Add dynamic state flags controlling whether TBIMR is enabled dur...Francisco Jerez5-1/+33
2023-10-27intel/xehp+: Import algorithm for TBIMR tiling parameter calculation.Francisco Jerez2-0/+276
2023-10-27intel/xehp+: Add TBIMR-related genxml definitions.Francisco Jerez1-0/+41
2023-09-05intel/dev/xe: Move placeholder subslice info into XEHP_FEATURESJordan Justen1-2/+1
2023-07-14iris: migrate WA 14013910100 to use the WA frameworkRohan Garg1-2/+3
2023-05-15iris: Init CCS_E to COMPRESSED_NO_CLEAR for XeHPNanley Chery1-7/+20
2023-03-23intel/devinfo: dedicated entries for XeHPLionel Landwerlin1-2/+31
2022-11-02intel/dev: Set has_lsc in XEHP_FEATURES rather than DG2_FEATURESJordan Justen1-1/+1
2022-10-28iris: Enable INTEL_MEASURE for compute dispatches on XeHPNanley Chery1-0/+2
2022-08-23intel/fs: fixup scratch load/store handling on Gfx12.5+Lionel Landwerlin1-32/+34
2022-07-28intel/eu: Mark header present in URB memory fences on XeHPKenneth Graunke1-1/+1
2022-07-28intel/eu: Clarify spec citations for XeHP region restrictionsKenneth Graunke1-3/+8
2022-07-28intel/eu: Fix XeHP register region validation for hstride == 0Kenneth Graunke1-7/+22
2022-06-24iris: Update comment about 2GB dynamic state rangeKenneth Graunke1-4/+9
2022-06-15anv: Move STATE_BASE_ADDRESS programming into init_common_queue_state()Jordan Justen1-32/+32
2022-06-12intel/fs/xehp+: Emit scheduling fence for all NIR barriers on platforms with ...Francisco Jerez1-2/+4
2022-05-27intel: Only set VectorMaskEnable when neededJason Ekstrand6-9/+29
2022-05-26intel/disasm: add missing handling of <1;1,0>Lionel Landwerlin1-0/+1
2022-05-25intel/compiler: Move spill/fill tracking to the register allocatorKenneth Graunke5-34/+47
2022-05-17intel/perf: deal with OA reports timestamp values on DG2Lionel Landwerlin3-4/+24
2022-05-17intel/decoder: Fix binding table pointer decoding with large offsetsKenneth Graunke1-3/+16
2022-05-12anv: Fix INTEL_DEBUG=bat on XeHPKenneth Graunke1-0/+5
2022-05-02intel/compiler: In XeHP prefer <1;1,0> regions before compactingCaio Oliveira1-0/+24
2022-04-30intel/dev: Compute pixel pipe information based on geometry topology DRM query.Francisco Jerez1-28/+41
2022-04-28isl,iris: Add DG2 CCS modifier support for XeHPNanley Chery2-1/+68
2022-04-28isl,iris: Add I915_FORMAT_MOD_4_TILED support for XeHPAnuj Phogat2-0/+15
2022-04-25intel: fixup number of threads per EU on XeHPLionel Landwerlin1-0/+1
2022-04-07intel/compiler: Fix sample_d messages on DG2Ian Romanick1-3/+16
2022-03-31nir: intel/compiler: Lower TXD on array surfaces on DG2+Ian Romanick3-2/+9
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-27 00:12:05 +0000