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2021-06-07amdgpu/winsys: remove amdgpu_cs_has_chainingPierre-Eric Pelloux-Prayer2-13/+10
2021-06-07winsys/amdgpu: don't read bo->u.slab.entry after pb_slab_freePierre-Eric Pelloux-Prayer1-8/+4
2021-06-07radeonsi: dirty msaa_config on rs->multisample_enable changePierre-Eric Pelloux-Prayer1-0/+2
2021-06-07v3dv: expose VK_KHR_storage_buffer_storage_classIago Toral Quiroga2-1/+2
2021-06-07v3dv: document VK_KHR_relaxed_block_layout as implementedIago Toral Quiroga1-1/+1
2021-06-07d3d12: Add mechanism for D3D12 Adapter SelectionSteve Pronovost2-8/+59
2021-06-06nv50: expose GL ES 3.1 for nva3+ hardwareIlia Mirkin2-1/+3
2021-06-06nv50: expose images/buffers/computeIlia Mirkin1-9/+13
2021-06-06st/mesa: allow hardware to claim ES 3.1 without hw indirect drawsIlia Mirkin1-0/+9
2021-06-06mesa/get: allow image/buffer/atomic variables to be fetched in es3.1Ilia Mirkin4-29/+40
2021-06-06st/mesa: properly encode OES_geometry_shader requirementIlia Mirkin1-5/+3
2021-06-06mesa: relax ES 3.1 compute shader requirementsIlia Mirkin1-5/+12
2021-06-06st/mesa: avoid enabling image/buffer/compute extensions for weak hardwareIlia Mirkin1-5/+7
2021-06-06nouveau: improve video limit reportingIlia Mirkin2-4/+63
2021-06-06vdpau: allow state tracker to report a lower number of macroblocksIlia Mirkin2-2/+7
2021-06-06nvc0: fix 3d imagesIlia Mirkin2-16/+117
2021-06-06nv50: fix streamout queriesIlia Mirkin1-18/+22
2021-06-05v3dv: Fix assert.Vinson Lee1-1/+1
2021-06-05venus: unify VkNativeBufferANDROID and AHardwareBuffer image create infoYiwei Zhang1-74/+60
2021-06-05venus: refactor gralloc buffer and drm modifier properties queryYiwei Zhang3-70/+82
2021-06-05agx: Handle load_back_face_agxAlyssa Rosenzweig1-0/+3
2021-06-05agx: Lower front face to back faceAlyssa Rosenzweig1-0/+23
2021-06-05agx: Pack SR immediateAlyssa Rosenzweig1-0/+3
2021-06-05agx: List sr enum in PythonAlyssa Rosenzweig2-6/+23
2021-06-05agx: Generate enums from PythonAlyssa Rosenzweig2-2/+16
2021-06-05agx: Model get_srAlyssa Rosenzweig1-0/+3
2021-06-05asahi: Mark special fragment inputs as sysvalsAlyssa Rosenzweig1-2/+3
2021-06-05nir: Add nir_intrinsic_load_back_face_agxAlyssa Rosenzweig1-0/+3
2021-06-05freedreno/regs: split old/not used phy registers to separate DBDmitry Baryshkov3-64/+76
2021-06-05freedreno: Don't return a flushed batchRob Clark1-3/+9
2021-06-05freedreno: Fix typoRob Clark1-1/+1
2021-06-05i915: Implement __DRI2_FLUSH version 4Ville Syrjälä1-5/+19
2021-06-05i915: Implement __DRI_IMAGE_ATTRIB_OFFSET queryVille Syrjälä1-1/+4
2021-06-04intel/isl: Fix isl_format_is_validJason Ekstrand1-1/+6
2021-06-04nir: define NIR_ALU_MAX_INPUTSHoe Hao Cheng1-2/+7
2021-06-04util/ra: Use the conflicting neighbor to skip unavailable registers.Emma Anholt1-5/+18
2021-06-04lima: Use ra_alloc_contig_reg_class().Eric Anholt1-91/+16
2021-06-04intel/vec4: Use ra_alloc_contig_reg_class() to reduce RA overhead.Eric Anholt2-53/+7
2021-06-04intel/fs: Use ra_alloc_contig_reg_class() to speed up RA.Eric Anholt2-163/+19
2021-06-04v3d: Use the ra_alloc_contig_reg_class() function to speed up RA.Eric Anholt1-5/+5
2021-06-04vc4: Use the ra_alloc_contig_reg_class() function to speed up RA.Eric Anholt1-7/+7
2021-06-04ra: Add fast-path support for register classes of contiguous regs.Eric Anholt4-40/+283
2021-06-04ra: Use struct ra_class in the public API.Eric Anholt18-116/+126
2021-06-04ra: Document that class index is allocated in order, use that in r300.Eric Anholt2-2/+2
2021-06-04ra: Add a unit test.Eric Anholt4-144/+278
2021-06-04intel: properly constify isl_format_layoutsAdam Jackson3-5/+19
2021-06-04zink: explicitly advertise index buffer format supportMike Blumenkrantz1-0/+7
2021-06-04d3d12: explicitly advertise index buffer format supportMike Blumenkrantz1-3/+6
2021-06-04r600: explicitly advertise index buffer format supportErik Faye-Lund3-0/+23
2021-06-04r300: explicitly advertise index buffer format supportMike Blumenkrantz1-0/+7
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