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AgeCommit message (Expand)AuthorFilesLines
2020-04-04glsl: don't limit fp16 lowering to fragRob Clark1-1/+1
2020-04-04freedreno: limit fp16 to frag and computeRob Clark1-0/+2
2020-04-04freedreno/ir3: also precompile compute shaders for shaderdbRob Clark1-0/+10
2020-04-04freedreno: fix missing lockingRob Clark1-0/+2
2020-04-04freedreno/a6xx: add some compute loggingRob Clark2-2/+21
2020-04-04freedreno/ir3/cf: use ssa-usesRob Clark1-25/+23
2020-04-04freedreno/ir3: add a pass to collect SSA usesRob Clark2-0/+37
2020-04-04freedreno/ir3/cf: skip array load/storeRob Clark1-0/+5
2020-04-04freedreno/ir3: fixup cat3 32b vs 16bRob Clark1-33/+15
2020-04-04freedreno/ir3/cf: handle widening tooRob Clark1-6/+32
2020-04-04nir: fix definition of imadsh_mix16 for vectorsRob Clark1-3/+3
2020-04-03aco: use MUBUF to load subdword SSBODaniel Schürmann1-2/+2
2020-04-03aco: implement 8bit/16bit store_ssboDaniel Schürmann1-8/+31
2020-04-03aco: implement 8bit/16bit load_bufferDaniel Schürmann1-12/+100
2020-04-03aco: implement storagePushConstant8 & storagePushConstant16Daniel Schürmann1-4/+22
2020-04-03aco: implement vec2/3/4 with subdword operandsDaniel Schürmann1-6/+30
2020-04-03aco: prepare helper functions for subdword handlingDaniel Schürmann1-10/+46
2020-04-03aco: add byte_align_scalar() & trim_subdword_vector() helper functionsDaniel Schürmann1-0/+76
2020-04-03aco: add missing conversion operations for small bitsizesDaniel Schürmann2-14/+190
2020-04-03aco: don't vectorize 8/16bit load/store_ssboDaniel Schürmann1-2/+7
2020-04-03aco: don't assume split_vector(create_vector) has the same number of elements...Daniel Schürmann1-1/+2
2020-04-03aco: don't propagate SGPRs into subdword PSEUDO instructionsDaniel Schürmann1-2/+6
2020-04-03aco: lower subdword shuffles correctly.Daniel Schürmann1-70/+124
2020-04-03aco: add builder function for subdword copy()Daniel Schürmann1-5/+15
2020-04-03aco: small refactoring of shuffle code loweringDaniel Schürmann1-41/+48
2020-04-03aco: align subdword registers during RA when necessaryDaniel Schürmann1-0/+24
2020-04-03aco: adapt register allocation for subdword registersDaniel Schürmann1-8/+47
2020-04-03aco: create helper function to collect variables from register areaDaniel Schürmann1-24/+35
2020-04-03aco: add notion of subdword registers to register allocatorDaniel Schürmann1-24/+75
2020-04-03aco: remove unnecessary reg_file.fill() operation in get_reg_create_vector()Daniel Schürmann1-6/+5
2020-04-03aco: fix Temp and assignment of renamed operands during RADaniel Schürmann1-1/+2
2020-04-03aco: print subdword registersDaniel Schürmann1-14/+19
2020-04-03aco: validate RA of subdword assignmentsDaniel Schürmann1-21/+22
2020-04-03aco: validate uninitialized operandsDaniel Schürmann1-0/+2
2020-04-03aco: validate register alignment of subdword operands and definitionsDaniel Schürmann1-0/+8
2020-04-03aco: validate p_create_vector with subdword elements properlyDaniel Schürmann1-2/+3
2020-04-03aco: refactor regClass setup for subdword VGPRsDaniel Schürmann2-92/+35
2020-04-03aco: add emission support for register-allocated sdwa selsRhys Perry2-5/+27
2020-04-03aco: add sub-dword regclassesDaniel Schürmann2-1/+37
2020-04-03aco: print and validate opselRhys Perry2-2/+18
2020-04-03aco: add SDWA_instructionRhys Perry5-7/+207
2020-04-03aco: add comparison operators for PhysRegDaniel Schürmann1-0/+3
2020-04-03aco: make PhysReg in units of bytesRhys Perry6-38/+40
2020-04-03nir: fix unpack_64_4x16 in lower_alu_to_scalar()Daniel Schürmann1-0/+1
2020-04-03drm-shim: stub libdrm's use of realpath()Lionel Landwerlin1-0/+22
2020-04-03drm-shim: return device platform as specifiedLionel Landwerlin7-4/+30
2020-04-03spirv: Rewrite CFG constructionJason Ekstrand2-294/+503
2020-04-03spirv: Add a parent field to vtn_cf_nodeJason Ekstrand2-10/+21
2020-04-03spirv: Make vtn_function a vtn_cf_nodeJason Ekstrand3-6/+11
2020-04-03spirv: Make vtn_case a vtn_cf_nodeJason Ekstrand2-8/+15
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