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2019-12-12VERSION: bump for 19.3.0 finalmesa-19.3.0Dylan Baker1-1/+1
2019-12-12docs: add release notes for 19.3.0Dylan Baker1-0/+3138
2019-12-12Revert "egl: move #include of local headers out of Khronos headers"Dylan Baker3-4/+3
This reverts commit 87efb9f3a4f366372bc873dee741a2c2f272e5c9. This is breaking the QT build, so it needs to go until these symbols can make their way to upstream khronos
2019-12-12Revert "egl: avoid local modifications for eglext.h Khronos standard header ↵Dylan Baker2-11/+11
file" This reverts commit 2a497735ec75cfc5edaff378613e3b145b3bb22d. This patch is built on the previous patch, which needs to be reverted.
2019-12-12anv: fix incorrect VMA alignment for CCS main surfacesLionel Landwerlin1-2/+12
Maybe finer way of dealing with this requirement would be to increase the number of pdevice->memory.types[] to add a category for special alignment cases. Meanwhile this fixes the problem of CCS surface alignment and it's probably not going to cause issues given the size of our address space. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 6af8a4acc4a4 ("anv: Add aux-map translation for gen12+") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 5fdea9f40182002899fc941bfb8c3f36ed5366a1)
2019-12-12ac/nir: fix out-of-bound access when loading constants from globalSamuel Pitoiset1-4/+14
Global load/store instructions can't know if the offset is out-of-bound because they don't use descriptors (no range). Fix this by clamping the offset for arrays that are indexed with a non-constant offset that's greater or equal to the array size. This fixes VM faults and GPU hangs with Dead Rising 4. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2148 Fixes: 71a67942003 ("ac/nir: Enable nir_opt_large_constants") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit a0f1a5fa051786c16de6f0062771051f8565daec)
2019-12-12radeonsi: use gfx9.surf_offset to compute texture offsetPierre-Eric Pelloux-Prayer1-1/+2
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2177 Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit ff0f10866699a22216fd1a4af6cdb89c2fea10e1)
2019-12-11android: radeonsi: fix build after vl refactoring (v2)Mauro Rossi3-3/+16
vl functions moved from radeonsi to gallium/auxiliary/vl have left android build of radeonsi in broken state. libmesa_galliumvl static is need to build readeonsi, gallium_dri building rules are reworked to avoid multiple symbols and libmesa_galliumvl static dependency is needed in radeonsi. Here is the changelog: - android: gallium/auxiliary: add libmesa_galliumvl static - android: gallium_dri: move libmesa_gallium to static to prevent multiple symbols - android: radeonsi: fix build after vl refactoring Fixes the following building error: external/mesa/src/gallium/drivers/radeonsi/si_uvd.c:47: error: undefined reference to 'vl_video_buffer_create_as_resource' clang.real: error: linker command failed with exit code 1 (use -v to see invocation) Fixes: 86e60bc ("radeonsi: remove si_vid_join_surfaces and use combined planar allocations") Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 96aef08dc6f4ea4a79cdf995d867d08e8f838b2a) Conflicts Resolved by Dylan Baker Conflicts: src/gallium/targets/dri/Android.mk Panfrost is not enabled for android in 19.3, and the series is a bit bigger than I'd like to pull into the stable branch for a .0 release
2019-12-11anv: Don't leak when set_tiling failsJason Ekstrand1-3/+4
Fixes: a44744e01d73 "anv: Require a dedicated allocation for..." Reviewed-by: Ivan Briano <ivan.briano@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 0a36fafa95175efbad1a61b36706e535929afd2b) Conflicts resolved by Dylan Baker Conflicts: src/intel/vulkan/anv_device.c
2019-12-11iris: Fix import of multi-planar surfaces with modifiersNanley Chery2-1/+12
Multi-planar surfaces are allowed to have modifiers. Don't require DRM_FORMAT_MOD_INVALID in order to create a surface for each plane defined by the format. Fixes: 246eebba4a8 ("iris: Export and import surfaces with modifiers that have aux data") Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 21376cffb37018160ad3eef38b5a640ba1675a4f)
2019-12-11iris: try to set the specified tiling when importing a dmabufJames Xiong3-11/+29
When importing a dmabuf with a specified tiling, the dmabuf user should always try to set the tiling mode because: 1) the exporter can set tiling AFTER exporting/importing. 2) a dmabuf could be exported from a kernel driver other than i915, in this case the dmabuf user and exporter need to set tiling separately. This patch fixes a problem when running vkmark under weston with iris on ICL, it crashed to console with the following assert. i965 doesn't have this problem as it always tries to set the specified tiling mode. weston: ../src/gallium/drivers/iris/iris_resource.c:990: iris_resource_from_handle: Assertion `res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)' failed. Signed-off-by: James Xiong <james.xiong@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> (cherry picked from commit b6d45e7f748e9ff7e198391f5ce5d1253101fedb)
2019-12-11gallium: Store the image format in winsys_handleNanley Chery2-0/+10
This format will be used to properly handle planar images with modifiers in iris. Fixes: 246eebba4a8 ("iris: Export and import surfaces with modifiers that have aux data") Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 51ee8fff9b5e803592a2fd34730fdcfdfba469cb)
2019-12-11radv: Fix RGBX Android<->Vulkan format correspondence.Bas Nieuwenhuizen1-1/+1
This is correct per the Vulkan spec format equivalence table. Fixes: f36b52740a0 "radv/android: Add android hardware buffer queries." Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 2e44bfc14f5c2e44ed820257615c2008955bc5bf)
2019-12-11meson/broadcom: libbroadcom_cle also needs zlibDylan Baker1-1/+1
Fixes: 1ae8018a6af81eec4832a57d9d0346aa3dd98d28 ("meson: Add support for the vc4 driver.") Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit d0eebda99088d15199aa0ae2c2d62ab6939568ce)
2019-12-11meson/broadcom: libbroadcom_cle needs expat headersDylan Baker1-1/+1
Fixes: 1ae8018a6af81eec4832a57d9d0346aa3dd98d28 ("meson: Add support for the vc4 driver.") Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 85a9698ac3a032aa8e2e71ff804b489749a754ec)
2019-12-10anv: fix missing gen12 handlingLionel Landwerlin1-0/+3
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 181be14d4303 ("anv: Build for gen12") Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit dcfe1903c3f501429851d0278ba78742e907355b)
2019-12-10radeonsi: fix multi plane buffers creationPierre-Eric Pelloux-Prayer1-2/+4
When using 3 planes, the sequence produces this chain: plane0 -> plane2 This commit fixes this to produce: plane0 -> plane1 -> plane2 Fixes: 86e60bc2659 ("radeonsi: remove si_vid_join_surfaces and use combined planar allocations") Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2193 Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit e3e91cebcd9307654eb3535e2f6521103ec8b997)
2019-12-10gallium/util: Support POLYGON in u_stream_outputs_for_verticesAlyssa Rosenzweig1-1/+8
u_decomposed_prims_for_vertices cannot support POLYGON, but POLYGON is trivial to support as a special case directly (since we have the number of vertices directly). Fixes aborts in Panfrost in apps using GL_POLYGON. Fixes: e881aa8c12c ("gallium/util: Add u_stream_outputs_for_vertices helper") Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Revewied-by: Eric Anholt <eric@anholt.net> (cherry picked from commit a37822f5f740c55cd6f848adfd6c3d567ae4fd79)
2019-12-10anv: Re-emit all compute state on pipeline switchJason Ekstrand1-0/+7
It's a very odd case to hit in the real world. However, there are some CTS tests which switch back and forth between dispatch and clear without changing the pipeline. Fixes: bc612536eb2f "anv: Emit a dummy MEDIA_VFE_STATE before switching..." Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> (cherry picked from commit 0f60aa4037dfb6aa86d5b9524fe649f13b2b8825)
2019-12-10freedreno: reorder format checkFritz Koenig3-6/+6
With the addition of the planar formats helper, the planar formats no longer have a valid block.bits field. Calling util_format_get_blocksize therefore asserts. Reorder the check to see if the format is supported before doing the query to get the blocksize. Fixes: 20f132e5eff2d ("gallium/util: add planar format layouts and helpers") Signed-off-by: Fritz Koenig <frkoenig@google.com> Reviewed-by: Rob Clark <robdclark@chromium.org> (cherry picked from commit c496d442844183968f7c4903c8ed549aa990d15f)
2019-12-10gallium/dri2: Fix creation of multi-planar modifier imagesNanley Chery1-19/+16
The commit noted below assumed and enforced that DRM_MOD_INVALID was the only valid modifier for multi-planar imported images. Due to that, it required that modifier on multi-planar images to: 1. Allow multiple planes. 2. Perform YUV format lowering and extent adjustments. 3. Use buffer_index to correctly map the given planes. Fix these issues by removing or updating the code built on that assumption. Fixes: 2066966c106 ("gallium/dri2: Support creating multi-planar modifier images") Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit d5c857837aae205c0e1fddee30300b4419e2bb3f)
2019-12-10glsl/nir: iterate the system values list when adding varyingsTimothy Arceri1-25/+36
Iterate the system values list when adding varyings to the program resource list in the NIR linker. This is needed to avoid CTS regressions when using the NIR to build the GLSL resource list in an upcoming series. Presumably it also fixes a bug with the current ARB_gl_spirv support. Fixes: ffdb44d3a0a2 ("nir/linker: Add inputs/outputs to the program resource list") Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> (cherry picked from commit 1abca2b3c84a42ab64c466bc209db42c41bba5e3)
2019-12-10intel/compiler: Fix 'comparison is always true' warningIan Romanick1-2/+2
Without looking at the assembly or something, I'm not sure what the compiler does here. The brw_reg_type enum is marked packed, so I'm guess that it gets represented as a uint8_t. That's the only reason I could think that comparing with -1 would be always true. This patch adds the same cast that exists in brw_hw_type_to_reg_type. It might be better to add a #define outside the enum for BRW_REGISTER_TYPE_INVALID as (enum brw_reg_type)-1. src/intel/compiler/brw_eu_compact.c: In function ‘has_immediate’: src/intel/compiler/brw_eu_compact.c:1515:20: warning: comparison is always true due to limited range of data type [-Wtype-limits] 1515 | return *type != -1; | ^~ src/intel/compiler/brw_eu_compact.c:1518:20: warning: comparison is always true due to limited range of data type [-Wtype-limits] 1518 | return *type != -1; | ^~ Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> CID: 1455194 Fixes: 12d3b11908e ("intel/compiler: Add instruction compaction support on Gen12") Cc: @mattst88 (cherry picked from commit 668635abd26dda458f9293f99dd39f56431a4d61)
2019-12-10nir/lower_clip: Fix incorrect driver loc for clipdist outputsRob Clark1-0/+11
Somehow adjusting maxloc based on existing outputs got lost, resulting in the clipdist varying clobbering the position varying. Causing a shader that had no position output in freedreno/ir3, which triggers GPU hangs in neverball. Fixes: d0f746b6458 ("nir: Save nir_variable pointers in nir_lower_clip_vs rather than locs.") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit 372ed42d222a274abe712b62f4b037cbeb6fddb5)
2019-12-04cherry-ignore: update for 19.3-rc7Dylan Baker1-1/+2
2019-12-04intel/perf: fix improper pointer accessLionel Landwerlin1-1/+1
This expression was unused by the macro, probably why it didn't register in the compilation. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit ddacd3d43b203e7c66ec366820e2a230b7e3aa67)
2019-12-04intel/perf: simplify the processing of OA reportsLionel Landwerlin1-28/+36
This is a more accurate description of what happens in processing the OA reports. Previously we only had a somewhat difficult to parse state machine tracking the context ID. What we really only need to do to decide if the delta between 2 reports (r0 & r1) should be accumulated in the query result is : * whether the r0 is tagged with the context ID relevant to us * if r0 is not tagged with our context ID and r1 is: does r0 have a invalid context id? If not then we're in a case where i915 has resubmitted the same context for execution through the execlist submission port v2: Update comment (Ken) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 8c0b05826304370ef9e5f1e607d0f0305a0eb759)
2019-12-04intel/perf: take into account that reports read can be fairly oldLionel Landwerlin1-3/+4
If we read the OA reports late enough after the query happens, we can get a timestamp in the report that is significantly in the past compared to the start timestamp of the query. The current code must deal with the wraparound of the timestamp value (every ~6 minute). So consider that if the difference is greater than half that wraparound period, we're probably dealing with an old report and make the caller aware it should read more reports when they're available. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit b364e920bf8c6805bcc3ff1cedf6b77dbb61b1e0)
2019-12-04intel/perf: set read buffer len to 0 to identify empty bufferLionel Landwerlin1-2/+3
We always add an empty buffer in the list when creating the query. Let's set the len appropriately so that we can recognize it when we read OA reports up to the end of a query. We were using an 0 timestamp value associated with the empty buffer and incorrectly assuming this was a valid value. In turn that led to not reading enough reports and resulted in deltas added to our counter values which should have been discarded because those would be flagged for a different context. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 9d0a5c817ce21adabeda5153035b30609e2862b2)
2019-12-04intel/perf: fix invalid hw_id in query resultsLionel Landwerlin1-2/+6
Accumulation happens between 2 reports, it can be between a start/end report from another context. So only consider updating the hw_id of the results when it's not already valid and that we have a valid value to put in there. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 41b54b5faf ("i965: move OA accumulation code to intel/perf") Reviewed-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit acea59dbf8056b46444c820115d86c42d0411686)
2019-12-04VERSION: bump version for 19.3-rc6mesa-19.3.0-rc6Dylan Baker1-1/+1
2019-12-04aco: fix a couple of value numbering issuesDaniel Schürmann1-8/+14
Fixes: 3a20ef4a3299fddc886f9d5908d8b3952dd63a54 'aco: refactor value numbering' Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-03anv: Set up SBE_SWIZ properly for gl_ViewportJason Ekstrand1-2/+2
gl_Viewport is also in the VUE header so we need to whack the read offset to 0 and emit a default (no overrides) SBE_SWIZ entry in that case as well. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit b1f37688ba717db81a7e9c97e2a875d528d85112)
2019-12-03iris: Allow max dynamic pool size of 2GB for gen12Jordan Justen1-1/+9
Reworks: * Adjust comment to list the state packets that curro found to be affected. Fixes: 8125d7960b6 ("intel/dev: Add preliminary device info for Tigerlake") Cc: 19.3 <mesa-stable@lists.freedesktop.org> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> (cherry picked from commit e277009d8dbdc9aec4be26aed5357ec41f359937)
2019-12-03nir/lower_io_to_vector: don't create arrays when not neededRhys Perry1-1/+7
Some backends require that there are no array varyings. If there were no arrays in the input shader, the pass shouldn't have to create new ones. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2103 Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2167 Fixes: bcd14756eec ('nir/lower_io_to_vector: add flat mode') Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (cherry picked from commit 5404b7aaa36fad18df19e12abcc8af69014e74c2)
2019-12-03radv: set writes_memory for global memory stores/atomicsRhys Perry1-8/+25
Fixes: 13ab63bb62b ('radv: Implement VK_EXT_buffer_device_address.') Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 35fab1ba3395604f748cd13ba82991372ca0cae7)
2019-12-03aco: don't split live-ranges of linear VGPRsDaniel Schürmann1-4/+11
Fixes: 93c8ebfa780ebd1495095e794731881aef29e7d3 'aco: Initial commit of independent AMD compiler' Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> (cherry picked from commit 8861a82be7df2a5816254b45d390ddafad7d8711)
2019-12-03aco: add v_nop inbetween exec write and VMEM/DS/FLATRhys Perry1-5/+8
LLVM and the proprietary compiler seem to do this Fixes: b01847bd9 ("aco/gfx10: Fix mitigation of VMEMtoScalarWriteHazard.") Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (cherry picked from commit a9fc81b098ca36d063dbdb6f69ffde1ab215d34b)
2019-12-03aco: fix i2i64Rhys Perry1-2/+6
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler') Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (cherry picked from commit 11f43caaeca166c96ae49dbd506b6f58dd4a13fb)
2019-12-03aco: propagate p_wqm on an image_sample's coordinate p_create_vectorRhys Perry1-9/+12
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2156 Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler') Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (cherry picked from commit ff70ccad16a2efb3be1fbc4ca03453d38721a267)
2019-12-03etnaviv: remove dead codeChristian Gmeiner1-3/+0
ptiled is always NULL so the if statement is useless. CoverityID: 1415572 Fixes: b9627765303 ("etnaviv: rework compatible render base") CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> (cherry picked from commit 1be220833c18139ff9f3c7c9237deeb726ba5c55)
2019-12-03i965: update Makefile.sources for perf changesJonathan Gray1-2/+0
brw_performance_query_metrics.h was removed in 134e750e16bfc53480e0bba6f0ae3e1d2a7fb87c and brw_performance_query.h was removed in 8ae6667992ccca41d08884d863b8aeb22a4c4e65 remove reference to these files from Makefile.sources Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Fixes: 134e750e16bfc53480e0 ("i965: extract performance query metrics") Fixes: 8ae6667992ccca41d088 ("intel/perf: move query_object into perf") Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit 34dda0ca659a8dd4a25123d966ed04340b9a0e45)
2019-12-03panfrost: Make sure we reset the damage region of RTs at flush timeBoris Brezillon3-1/+23
We must reset the damage info of our render targets here even though a damage reset normally happens when the DRI layer swaps buffers. That's because there can be implicit flushes the GL app is not aware of, and those might impact the damage region: if part of the damaged portion is drawn during those implicit flushes, you have to reload those areas before next draws are pushed, and since the driver can't easily know what's been modified by the draws it flushed, the easiest solution is to reload everything. Reported-by: Carsten Haitzler <raster@rasterman.com> Fixes: 65ae86b85422 ("panfrost: Add support for KHR_partial_update()") Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> (cherry picked from commit c6e2096c47f05aab6807325799bf0b6a4092084d)
2019-12-03gallium: Fix the ->set_damage_region() implementationBoris Brezillon3-4/+35
BACK_LEFT attachment can be outdated when the user calls KHR_partial_update() (->lastStamp != ->texture_stamp), leading to a damage region update on the wrong pipe_resource object. Let's delay the ->set_damage_region() call until the attachments are updated when we're in that case. Reported-by: Carsten Haitzler <raster@rasterman.com> Fixes: 492ffbed63a2 ("st/dri2: Implement DRI2bufferDamageExtension") Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit b196e1a8cfbd2c6b53f688542bcda5bb8f7f8888)
2019-12-03radv: Fix timeline semaphore refcounting.Bas Nieuwenhuizen1-9/+4
Was totally broken ... Removed two if(point) {} because point is always non-NULL and we were counting on that already for counting, since we NULL our references to semaphores without active point earlier. Fixes: 4aa75bb3bdd "radv: Add wait-before-submit support for timelines." Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2137 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 48fc65413c8607390b2ed8cdaccac490d8c8fdae)
2019-12-03winsys/amdgpu: avoid double simple_mtx_unlock()Jonathan Gray1-1/+0
pthread_mutex_unlock() when unlocked is documented by posix as being undefined behaviour. On OpenBSD pthread_mutex_unlock() will call abort(3) if this happens. This occurs in amdgpu_winsys_create() after cb446dc0fa5c68f681108f4613560543aa4cf553 winsys/amdgpu: Add amdgpu_screen_winsys Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org> Signed-off-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 3fe3bde4f2c8813e13fa2992212ca46a894e68b6)
2019-12-03radv: Unify max_descriptor_set_size.Bas Nieuwenhuizen1-14/+15
They were out of sync. Besides syncing, lets ensure they never diverge again. Fixes: 8d2654a4197 "radv: Support VK_EXT_inline_uniform_block." Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 4cde0e04e38ad2b9212d451cb5a84ed4ceaffd03)
2019-12-03drirc: Set vs_position_always_invariant for Shadow of Mordor on IntelKenneth Graunke1-0/+10
When drawing the main character in Shadow of Mordor, the game appears to draw Talion with one vertex shader, and the Wraith with another. If the compiler optimizes those in different ways which lead to slight imprecisions, then the resulting positions may not line up, leading to Z-fighting occurring as the game decides which of the two are in front. brw_nir_opt_peephole_ffma looks at usages of multiply adds across the entire shader, and may make different decisions between the two, leading to such imprecisions and Z-fighting. This started happening recently after a NIR change to eliminate unnecessary MOVs (7025dbe7), but that change simply exposed the existing problem. Improves performance on Skylake GT4e by 1.22945% +/- 0.398672% (n=3), likely due to the fixed rendering. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1985 Fixes: 7025dbe794b ("nir: Skip emitting no-op movs from the builder.") Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit 51cc380894b6c541ac3383336389242cf3f9fd67)
2019-12-03driconf, glsl: Add a vs_position_always_invariant optionKenneth Graunke8-0/+23
Many applications use multi-pass rendering and require their vertex shader position to be computed the same way each time. Optimizations may consider, say, fusing a multiply-add based on global usage of an expression in a shader. But a second shader with the same expression may have different code, causing that optimization to make the other choice the second time around. The correct solution is for applications to mark their VS outputs 'invariant', indicating they need multiple shaders to compute that output in the same manner. However, most applications fail to do so. So, we add a new driconf option - vs_position_always_invariant - which forces the gl_Position output in vertex shaders to be marked invariant. Fixes: 7025dbe794b ("nir: Skip emitting no-op movs from the builder.") Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit 9b577f2a887968483b88b629673d3f9904a179ff)
2019-12-03radv/gfx10: fix implementation of exclusive scansSamuel Pitoiset1-25/+58
This implementation is loosely based on ROCm. https://github.com/RadeonOpenCompute/ROCm-Device-Libs/blob/master/ockl/src/wfredscan.cl This fixes dEQP-VK.subgroups.arithmetic.*.subgroupexclusive* on GFX10. Fixes: 227c29a80de ("amd/common/gfx10: implement scan & reduce operations") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit c9aa843961d2c3cb34e7cb2dc843b93d723e0692) Conflicts resolved by Dylan Baker
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