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-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp_clear.cpp35
1 files changed, 11 insertions, 24 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 3f096b513fa..1904bde1726 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -265,30 +265,17 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
x_align *= 16;
y_align *= 32;
- if (brw->is_haswell) {
- /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
- * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
- * Clear of Non-MultiSampled Render Target Restrictions":
- *
- * [IVB, VLVT, HSW]: Clear rectangle must be aligned to two times
- * the number of pixels in the table shown below... x_align,
- * y_align values computed above are the relevant entries in the
- * referred table.
- *
- * We apply the workaround to only Haswell because (a) we suspect that
- * is the only hardware where it is actually required and (b) we
- * haven't yet validated the workaround for the other hardware.
- */
- x0 = ROUND_DOWN_TO(x0, 2 * x_align);
- y0 = ROUND_DOWN_TO(y0, 2 * y_align);
- x1 = ALIGN(x1, 2 * x_align);
- y1 = ALIGN(y1, 2 * y_align);
- } else {
- x0 = ROUND_DOWN_TO(x0, x_align);
- y0 = ROUND_DOWN_TO(y0, y_align);
- x1 = ALIGN(x1, x_align);
- y1 = ALIGN(y1, y_align);
- }
+ /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
+ * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
+ * Clear of Non-MultiSampled Render Target Restrictions":
+ *
+ * Clear rectangle must be aligned to two times the number of pixels in
+ * the table shown below due to 16x16 hashing across the slice.
+ */
+ x0 = ROUND_DOWN_TO(x0, 2 * x_align);
+ y0 = ROUND_DOWN_TO(y0, 2 * y_align);
+ x1 = ALIGN(x1, 2 * x_align);
+ y1 = ALIGN(y1, 2 * y_align);
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p327):