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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp12
1 files changed, 4 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index e5c0536d478..3d6a8f5a602 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1265,16 +1265,14 @@ fs_visitor::calculate_urb_setup()
continue;
if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
- int fp_index = _mesa_vert_result_to_frag_attrib((gl_varying_slot) i);
-
/* The back color slot is skipped when the front color is
* also written to. In addition, some slots can be
* written in the vertex shader and not read in the
* fragment shader. So the register number must always be
* incremented, mapped or not.
*/
- if (fp_index >= 0)
- urb_setup[fp_index] = urb_next;
+ if (_mesa_varying_slot_in_fs((gl_varying_slot) i))
+ urb_setup[i] = urb_next;
urb_next++;
}
}
@@ -3001,10 +2999,8 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
key.proj_attrib_mask |= BITFIELD64_BIT(i);
if (intel->gen < 6) {
- int vp_index = _mesa_vert_result_to_frag_attrib((gl_varying_slot) i);
-
- if (vp_index >= 0)
- key.vp_outputs_written |= BITFIELD64_BIT(vp_index);
+ if (_mesa_varying_slot_in_fs((gl_varying_slot) i))
+ key.vp_outputs_written |= BITFIELD64_BIT(i);
}
}