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-rw-r--r--src/freedreno/ci/freedreno-a630-fails.txt24
-rw-r--r--src/freedreno/drm/freedreno_bo_cache.c2
-rw-r--r--src/freedreno/vulkan/tu_clear_blit.c38
-rw-r--r--src/freedreno/vulkan/tu_pipeline.c4
-rw-r--r--src/freedreno/vulkan/tu_private.h9
-rw-r--r--src/freedreno/vulkan/tu_util.h6
6 files changed, 53 insertions, 30 deletions
diff --git a/src/freedreno/ci/freedreno-a630-fails.txt b/src/freedreno/ci/freedreno-a630-fails.txt
index e473c051b8b..364309fe096 100644
--- a/src/freedreno/ci/freedreno-a630-fails.txt
+++ b/src/freedreno/ci/freedreno-a630-fails.txt
@@ -601,27 +601,3 @@ spec@!opengl 2.1@pbo@test_polygon_stip,Fail
spec@!opengl 2.1@polygon-stipple-fs,Fail
spec@!opengl 3.0@clearbuffer-depth-cs-probe,Timeout
spec@!opengl 3.1@primitive-restart-xfb generated,Fail
-
-# Failures with unaligned gmem store
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
diff --git a/src/freedreno/drm/freedreno_bo_cache.c b/src/freedreno/drm/freedreno_bo_cache.c
index 0a70cb531f4..1dc02499fa1 100644
--- a/src/freedreno/drm/freedreno_bo_cache.c
+++ b/src/freedreno/drm/freedreno_bo_cache.c
@@ -142,7 +142,7 @@ find_in_bucket(struct fd_bo_bucket *bucket, uint32_t flags)
break;
if (entry->alloc_flags == flags) {
bo = entry;
- list_del(&bo->list);
+ list_delinit(&bo->list);
break;
}
}
diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c
index a3168d5fbe5..6caa31beb95 100644
--- a/src/freedreno/vulkan/tu_clear_blit.c
+++ b/src/freedreno/vulkan/tu_clear_blit.c
@@ -944,9 +944,15 @@ r3d_src_gmem(struct tu_cmd_buffer *cmd,
uint32_t desc[A6XX_TEX_CONST_DWORDS];
memcpy(desc, iview->view.descriptor, sizeof(desc));
- /* patch the format so that depth/stencil get the right format */
- desc[0] &= ~A6XX_TEX_CONST_0_FMT__MASK;
- desc[0] |= A6XX_TEX_CONST_0_FMT(tu6_format_texture(format, TILE6_2).fmt);
+ /* patch the format so that depth/stencil get the right format and swizzle */
+ desc[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK |
+ A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK |
+ A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK);
+ desc[0] |= A6XX_TEX_CONST_0_FMT(tu6_format_texture(format, TILE6_2).fmt) |
+ A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_X) |
+ A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_Y) |
+ A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_Z) |
+ A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_W);
/* patched for gmem */
desc[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
@@ -2687,6 +2693,7 @@ tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
*/
if (vk_format_is_depth_or_stencil(attachment->format)) {
tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS);
+ tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS);
tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH);
} else {
tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS);
@@ -2887,6 +2894,17 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
uint32_t gmem_offset,
uint32_t cpp)
{
+ /* RB_BIN_CONTROL/GRAS_BIN_CONTROL are normally only set once and they
+ * aren't set until we know whether we're HW binning or not, and we want to
+ * avoid a dependence on that here to be able to store attachments before
+ * the end of the renderpass in the future. Use the scratch space to
+ * save/restore them dynamically.
+ */
+ tu_cs_emit_pkt7(cs, CP_REG_TO_SCRATCH, 1);
+ tu_cs_emit(cs, CP_REG_TO_SCRATCH_0_REG(REG_A6XX_RB_BIN_CONTROL) |
+ CP_REG_TO_SCRATCH_0_SCRATCH(0) |
+ CP_REG_TO_SCRATCH_0_CNT(1 - 1));
+
r3d_setup(cmd, cs, format, VK_IMAGE_ASPECT_COLOR_BIT, 0, false,
iview->view.ubwc_enabled, dst_samples);
@@ -2907,6 +2925,9 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
/* sync GMEM writes with CACHE. */
tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
+ /* Wait for CACHE_INVALIDATE to land */
+ tu_cs_emit_wfi(cs);
+
r3d_run(cmd, cs);
/* Draws write to the CCU, unlike CP_EVENT_WRITE::BLIT which writes to
@@ -2915,6 +2936,17 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
* writes to depth images as a color RT, so there's no need to flush depth.
*/
tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS);
+
+ /* Restore RB_BIN_CONTROL/GRAS_BIN_CONTROL saved above. */
+ tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
+ tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_RB_BIN_CONTROL) |
+ CP_SCRATCH_TO_REG_0_SCRATCH(0) |
+ CP_SCRATCH_TO_REG_0_CNT(1 - 1));
+
+ tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
+ tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_GRAS_BIN_CONTROL) |
+ CP_SCRATCH_TO_REG_0_SCRATCH(0) |
+ CP_SCRATCH_TO_REG_0_CNT(1 - 1));
}
void
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 441ed0285fb..828f0f2c96d 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -2910,7 +2910,9 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
pipeline->line_mode = RECTANGULAR;
- if (tu6_primtype_line(pipeline->ia.primtype)) {
+ if (tu6_primtype_line(pipeline->ia.primtype) ||
+ (tu6_primtype_patches(pipeline->ia.primtype) &&
+ pipeline->tess.patch_type == IR3_TESS_ISOLINES)) {
const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_state =
vk_find_struct_const(rast_info->pNext,
PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
diff --git a/src/freedreno/vulkan/tu_private.h b/src/freedreno/vulkan/tu_private.h
index 28a9c5ea1c8..862d507c9dc 100644
--- a/src/freedreno/vulkan/tu_private.h
+++ b/src/freedreno/vulkan/tu_private.h
@@ -1068,7 +1068,14 @@ enum tu_cmd_flush_bits {
TU_CMD_FLAG_ALL_INVALIDATE =
TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
- TU_CMD_FLAG_CACHE_INVALIDATE,
+ TU_CMD_FLAG_CACHE_INVALIDATE |
+ /* Treat CP_WAIT_FOR_ME as a "cache" that needs to be invalidated when a
+ * a command that needs CP_WAIT_FOR_ME is executed. This means we may
+ * insert an extra WAIT_FOR_ME before an indirect command requiring it
+ * in case there was another command before the current command buffer
+ * that it needs to wait for.
+ */
+ TU_CMD_FLAG_WAIT_FOR_ME,
};
/* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty
diff --git a/src/freedreno/vulkan/tu_util.h b/src/freedreno/vulkan/tu_util.h
index 2ad7f86e36e..771a67a3416 100644
--- a/src/freedreno/vulkan/tu_util.h
+++ b/src/freedreno/vulkan/tu_util.h
@@ -99,6 +99,12 @@ tu6_primtype_line(enum pc_di_primtype type)
}
}
+static inline bool
+tu6_primtype_patches(enum pc_di_primtype type)
+{
+ return type >= DI_PT_PATCHES0 && type <= DI_PT_PATCHES31;
+}
+
static inline enum pc_di_primtype
tu6_primtype(VkPrimitiveTopology topology)
{
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-30 23:01:32 +0000