diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 8 |
3 files changed, 7 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 68c7ca11626..208c66a28f5 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -194,7 +194,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, surf[3] = pitch_bytes - 1; surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout); - if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { + if (surface->mt->mcs_mt) { gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt, is_render_target); } diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 6a7c8deff55..3164f994dd4 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -609,7 +609,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT | (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT; - if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { + if (irb->mt->mcs_mt) { gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit], irb->mt->mcs_mt, true /* is RT */); } diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h index d66d0b5a424..e2a7fe84f72 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h @@ -443,11 +443,13 @@ struct intel_mipmap_tree #ifndef I915 /** - * \brief MCS miptree for multisampled textures. + * \brief MCS miptree. * * This miptree contains the "multisample control surface", which stores - * the necessary information to implement compressed MSAA on Gen7+ - * (INTEL_MSAA_FORMAT_CMS). + * the necessary information to implement compressed MSAA + * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+. + * + * NULL if no MCS miptree is in use for this surface. */ struct intel_mipmap_tree *mcs_mt; |