diff options
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 20 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_meta.h | 19 |
3 files changed, 40 insertions, 1 deletions
diff --git a/.pick_status.json b/.pick_status.json index 0db950ca55a..f03e1a603e5 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1399,7 +1399,7 @@ "description": "radv: disable FMASK compression when drawing with GENERAL layout", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "96063100812d1de46f4146fde92975c98e78c3ce" }, diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 38c71dcd3ec..b0ef1e9a08e 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1365,6 +1365,13 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, cb_color_info &= C_028C70_DCC_ENABLE; } + if (!radv_layout_can_fast_clear(image, layout, in_render_loop, + radv_image_queue_family_mask(image, + cmd_buffer->queue_family_index, + cmd_buffer->queue_family_index))) { + cb_color_info &= C_028C70_COMPRESSION; + } + if (radv_image_is_tc_compat_cmask(image) && (radv_is_fmask_decompress_pipeline(cmd_buffer) || radv_is_dcc_decompress_pipeline(cmd_buffer))) { @@ -1374,6 +1381,19 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY; } + if (radv_image_has_fmask(image) && + (radv_is_fmask_decompress_pipeline(cmd_buffer) || + radv_is_hw_resolve_pipeline(cmd_buffer))) { + /* Make sure FMASK is enabled if it has been cleared because: + * + * 1) it's required for FMASK_DECOMPRESS operations to avoid + * GPU hangs + * 2) it's necessary for CB_RESOLVE which can read compressed + * FMASK data anyways. + */ + cb_color_info |= S_028C70_COMPRESSION(1); + } + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) { radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); radeon_emit(cmd_buffer->cs, cb->cb_color_base); diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h index f7b19477265..e3711aa4793 100644 --- a/src/amd/vulkan/radv_meta.h +++ b/src/amd/vulkan/radv_meta.h @@ -250,6 +250,25 @@ radv_is_dcc_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer) meta_state->fast_clear_flush.dcc_decompress_pipeline; } +/** + * Return whether the bound pipeline is the hardware resolve path. + */ +static inline bool +radv_is_hw_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer) +{ + struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state; + struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; + + for (uint32_t i = 0; i < NUM_META_FS_KEYS; ++i) { + VkFormat format = radv_fs_key_format_exemplars[i]; + unsigned fs_key = radv_format_meta_fs_key(format); + + if (radv_pipeline_to_handle(pipeline) == meta_state->resolve.pipeline[fs_key]) + return true; + } + return false; +} + /* common nir builder helpers */ #include "nir/nir_builder.h" |