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authorChad Versace <chad.versace@intel.com>2011-04-07 09:09:38 -0700
committerChad Versace <chad.versace@intel.com>2011-04-12 17:52:09 -0700
commitd3cc3901ab67823af3aba08efc863daa22ed1408 (patch)
treeaa161580ca22a1fc48d0633b32f36fce8ab6ff89 /src
parent4d7c1871671710865be3020e0d460e0463707f14 (diff)
i965: Change assertion condition from implicit to explicit
... because grokking explicit assertions requires fewer neurons. In brw_misc_state.c:emit_depthbuffer, change assertion condition tiling != I915_TILING_X && tiling != I915_TILING_NONE to tiling == I915_TILING_Y Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad.versace@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 74e911b4ddb..19eea07ebc6 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -248,8 +248,7 @@ static void emit_depthbuffer(struct brw_context *brw)
}
assert(region->tiling != I915_TILING_X);
- if (intel->gen >= 6)
- assert(region->tiling != I915_TILING_NONE);
+ assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));