diff options
| author | Alex Smith <asmith@feralinteractive.com> | 2017-03-30 21:03:58 +0200 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2017-04-12 13:30:22 +0100 |
| commit | b7d3c71d649348e0454c9a1a180cfeefcbea6452 (patch) | |
| tree | a197558c824e7bf8c4878fe63db43255266ab7b0 /src | |
| parent | a6114f0c4e619a1192062dc8dce91a67032faeb1 (diff) | |
radv: Invalidate L2 for TRANSFER_WRITE barriers
CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write
through L2. Therefore, to make these writes visible to later accesses
we must invalidate L2 rather than just writing it back, to avoid the
possibility that stale data is read through L2.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
[Bas: patch is a backport for 17.0 of the cherry-pick below]
(cherry picked from commit bc5d587a80b64fb3e0a5ea8067e6317fbca2bbc5)
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 628737c75ac..3aa415b152f 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2580,7 +2580,8 @@ void radv_CmdPipelineBarrier( flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB; break; case VK_ACCESS_TRANSFER_WRITE_BIT: - flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB; + flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | + RADV_CMD_FLAG_INV_GLOBAL_L2; break; default: break; |