diff options
| author | Rhys Perry <pendingchaos02@gmail.com> | 2021-04-05 14:26:33 +0100 |
|---|---|---|
| committer | Eric Engestrom <eric@engestrom.ch> | 2021-04-21 20:02:02 +0200 |
| commit | 70e8b11f37e027a34771c97ab834c4e741ea1b6f (patch) | |
| tree | bcea58dc1e4538ded6574e6c4c11cc6369ca7b54 /src | |
| parent | ef12d4ebb4f338b6108ce54eca1ad985842ce8f2 (diff) | |
ac/nir: set TRUNC_COORD=0 for nir_texop_tg4
Fixes black squares in Assassin's Creed: Valhalla and rendering of
FidelityFX-CACAO demo.
shader-db (sienna cichlid):
Totals:
SGPRS: 2977068 -> 2977220 (0.01 %)
VGPRS: 1929624 -> 1929616 (-0.00 %)
Spilled SGPRs: 5769 -> 5769 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 61423092 -> 61424672 (0.00 %) bytes
Max Waves: 895765 -> 895766 (0.00 %)
Totals from affected shaders:
SGPRS: 9520 -> 9672 (1.60 %)
VGPRS: 7464 -> 7456 (-0.11 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 527432 -> 529012 (0.30 %) bytes
Max Waves: 1819 -> 1820 (0.05 %)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Fixes: 58f25098a0d ("radv: Use TRUNC_COORD on samplers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10036>
(cherry picked from commit 6a7b89c89df9acea080ccc4f7c2852699ba3a0f9)
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/llvm/ac_nir_to_llvm.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index fc61447d81d..cd69c3c9d8a 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -4625,6 +4625,13 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr) } } + /* Set TRUNC_COORD=0 for textureGather(). */ + if (instr->op == nir_texop_tg4) { + LLVMValueRef dword0 = LLVMBuildExtractElement(ctx->ac.builder, args.sampler, ctx->ac.i32_0, ""); + dword0 = LLVMBuildAnd(ctx->ac.builder, dword0, LLVMConstInt(ctx->ac.i32, C_008F30_TRUNC_COORD, 0), ""); + args.sampler = LLVMBuildInsertElement(ctx->ac.builder, args.sampler, dword0, ctx->ac.i32_0, ""); + } + assert(instr->dest.is_ssa); args.d16 = instr->dest.ssa.bit_size == 16; args.tfe = instr->is_sparse; |