diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2011-08-12 18:27:16 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-01-30 09:46:00 -0800 |
| commit | 871da78263673cf123e28b3c0aa88b48745ac93d (patch) | |
| tree | 1ea78bb2134b271c26167064de8b4b797fd64253 /src/mesa | |
| parent | d02343e5016a5795451af3e0315b658b39463a30 (diff) | |
i965: Add chipset limits for Haswell GT1/GT2.
The maximum number of URB entries come from the 3DSTATE_URB_VS and
3DSTATE_URB_GS state packet documentation; the thread count information
comes from the 3DSTATE_VS and 3DSTATE_PS state packet documentation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
(cherry picked from commit 9add4e803877f97ad7f6d479d81d537426f09b6f)
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 1688bb1d57c..a6a5e4f1b39 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -290,7 +290,23 @@ brwCreateContext(int api, } /* WM maximum threads is number of EUs times number of threads per EU. */ - if (intel->gen >= 7) { + assert(intel->gen <= 7); + + if (intel->is_haswell) { + if (intel->gt == 1) { + brw->max_wm_threads = 102; + brw->max_vs_threads = 70; + brw->urb.size = 128; + brw->urb.max_vs_entries = 640; + brw->urb.max_gs_entries = 256; + } else if (intel->gt == 2) { + brw->max_wm_threads = 204; + brw->max_vs_threads = 280; + brw->urb.size = 256; + brw->urb.max_vs_entries = 1664; + brw->urb.max_gs_entries = 640; + } + } else if (intel->gen == 7) { if (intel->gt == 1) { brw->max_wm_threads = 48; brw->max_vs_threads = 36; |