diff options
| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2017-06-13 09:29:42 -0700 |
|---|---|---|
| committer | Andres Gomez <agomez@igalia.com> | 2017-06-28 20:15:02 +0300 |
| commit | 7d4dcbcad94ee90d22cd127b7e1c8f17992c47df (patch) | |
| tree | 7e2499e9bf2beaa5bfa36b34552d1b1022a00fbd /src/mesa/drivers | |
| parent | ea294dd259f52c8e98714bad535a1848db95f649 (diff) | |
i965/blorp: Do an end-of-pipe sync around CCS ops
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 314ec7b46ffa1640c0d9448e7752c2d7f6c18734)
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.c | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index e09a0fcdb53..e550ce5910b 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -887,9 +887,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, * and again afterwards to ensure that the resolve is complete before we * do any more regular drawing. */ - brw_emit_pipe_control_flush(brw, - PIPE_CONTROL_RENDER_TARGET_FLUSH | - PIPE_CONTROL_CS_STALL); + brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); struct blorp_batch batch; blorp_batch_init(&brw->blorp, &batch, brw, 0); @@ -899,9 +897,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, x0, y0, x1, y1); blorp_batch_finish(&batch); - brw_emit_pipe_control_flush(brw, - PIPE_CONTROL_RENDER_TARGET_FLUSH | - PIPE_CONTROL_CS_STALL); + brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); /* Now that the fast clear has occurred, put the buffer in * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing @@ -1001,9 +997,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt, * and again afterwards to ensure that the resolve is complete before we * do any more regular drawing. */ - brw_emit_pipe_control_flush(brw, - PIPE_CONTROL_RENDER_TARGET_FLUSH | - PIPE_CONTROL_CS_STALL); + brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); struct blorp_batch batch; @@ -1014,9 +1008,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt, blorp_batch_finish(&batch); /* See comment above */ - brw_emit_pipe_control_flush(brw, - PIPE_CONTROL_RENDER_TARGET_FLUSH | - PIPE_CONTROL_CS_STALL); + brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); } static void |