diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-08-10 12:06:37 -0300 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-05-09 15:11:53 -0700 |
| commit | f1d2b373177dbbb582cefb0d6c88994073fab652 (patch) | |
| tree | a42aa7b9370704654fcc4271b7a5198f602f8f56 /src/mesa/drivers/dri/intel/intel_context.c | |
| parent | d0b82b1add5d1d1419d4390a3f7c584b6ee7d92c (diff) | |
i965: make GT3 machines work as GT3 instead of GT2
We were not allowed to say the "GT3" name, but we really needed to
have the PCI IDs because too many people had such machines, so we had
to make the GT3 machines work as GT2.
Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :)
NOTE: This is a candidate for stable branches.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_context.c')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 0a1dd7501de..88cc2478f52 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -195,44 +195,44 @@ intelGetString(struct gl_context * ctx, GLenum name) break; case PCI_CHIP_HASWELL_GT1: case PCI_CHIP_HASWELL_GT2: - case PCI_CHIP_HASWELL_GT2_PLUS: + case PCI_CHIP_HASWELL_GT3: case PCI_CHIP_HASWELL_SDV_GT1: case PCI_CHIP_HASWELL_SDV_GT2: - case PCI_CHIP_HASWELL_SDV_GT2_PLUS: + case PCI_CHIP_HASWELL_SDV_GT3: case PCI_CHIP_HASWELL_ULT_GT1: case PCI_CHIP_HASWELL_ULT_GT2: - case PCI_CHIP_HASWELL_ULT_GT2_PLUS: + case PCI_CHIP_HASWELL_ULT_GT3: case PCI_CHIP_HASWELL_CRW_GT1: case PCI_CHIP_HASWELL_CRW_GT2: - case PCI_CHIP_HASWELL_CRW_GT2_PLUS: + case PCI_CHIP_HASWELL_CRW_GT3: chipset = "Intel(R) Haswell Desktop"; break; case PCI_CHIP_HASWELL_M_GT1: case PCI_CHIP_HASWELL_M_GT2: - case PCI_CHIP_HASWELL_M_GT2_PLUS: + case PCI_CHIP_HASWELL_M_GT3: case PCI_CHIP_HASWELL_SDV_M_GT1: case PCI_CHIP_HASWELL_SDV_M_GT2: - case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS: + case PCI_CHIP_HASWELL_SDV_M_GT3: case PCI_CHIP_HASWELL_ULT_M_GT1: case PCI_CHIP_HASWELL_ULT_M_GT2: - case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS: + case PCI_CHIP_HASWELL_ULT_M_GT3: case PCI_CHIP_HASWELL_CRW_M_GT1: case PCI_CHIP_HASWELL_CRW_M_GT2: - case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS: + case PCI_CHIP_HASWELL_CRW_M_GT3: chipset = "Intel(R) Haswell Mobile"; break; case PCI_CHIP_HASWELL_S_GT1: case PCI_CHIP_HASWELL_S_GT2: - case PCI_CHIP_HASWELL_S_GT2_PLUS: + case PCI_CHIP_HASWELL_S_GT3: case PCI_CHIP_HASWELL_SDV_S_GT1: case PCI_CHIP_HASWELL_SDV_S_GT2: - case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS: + case PCI_CHIP_HASWELL_SDV_S_GT3: case PCI_CHIP_HASWELL_ULT_S_GT1: case PCI_CHIP_HASWELL_ULT_S_GT2: - case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS: + case PCI_CHIP_HASWELL_ULT_S_GT3: case PCI_CHIP_HASWELL_CRW_S_GT1: case PCI_CHIP_HASWELL_CRW_S_GT2: - case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS: + case PCI_CHIP_HASWELL_CRW_S_GT3: chipset = "Intel(R) Haswell Server"; break; default: @@ -684,6 +684,8 @@ intelInitContext(struct intel_context *intel, intel->gt = 1; else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID)) intel->gt = 2; + else if (IS_HSW_GT3(devID)) + intel->gt = 3; else intel->gt = 0; |