diff options
| author | Nanley Chery <nanley.g.chery@intel.com> | 2016-09-30 16:28:53 -0700 |
|---|---|---|
| committer | Nanley Chery <nanley.g.chery@intel.com> | 2016-10-31 13:20:05 -0700 |
| commit | e9a25e024757c8daa0da86d064afd446824160dc (patch) | |
| tree | 01c606356cd65828a953a01fc599ae83df1e345b /src/mesa/drivers/dri/i965/brw_state_upload.c | |
| parent | 477ea60b68d3e9a16d1f4947f95e3e7ce20e6f67 (diff) | |
i965: Move gen8_disable_stages to brw_upload_initial_gpu_state
3DSTATE_WM_CHROMAKEY isn't programmed anywhere else.
3DSTATE_WM_HZ_OP is programmed, then cleared by blorp during a
HZ op, so repeatedly clearing it after every blorp execution is
redundant.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_state_upload.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 2461ee5800c..b689ae41f67 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -332,7 +332,6 @@ static const struct brw_tracked_state *gen8_render_atoms[] = &brw_gs_samplers, &gen8_multisample_state, - &gen8_disable_stages, &gen8_vs_state, &gen8_hs_state, &gen7_te_state, @@ -411,6 +410,19 @@ brw_upload_initial_gpu_state(struct brw_context *brw) if (brw->gen >= 8) { gen8_emit_3dstate_sample_pattern(brw); + + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_WM_CHROMAKEY << 16 | (2 - 2)); + OUT_BATCH(0); + ADVANCE_BATCH(); } } |