diff options
| author | Rhys Perry <pendingchaos02@gmail.com> | 2019-11-28 11:30:55 +0000 |
|---|---|---|
| committer | Dylan Baker <dylan@pnwbakers.com> | 2019-12-03 10:24:23 -0800 |
| commit | f7d100caad4ca170f9d2dacf02bf5e8d7cffe918 (patch) | |
| tree | 024e0be986b4f4c009b8723d21250733ef85a93a /src/amd/vulkan/radv_shader_info.c | |
| parent | 0fa0b5fc3a88d6df13663818423a184d4e9589fa (diff) | |
radv: set writes_memory for global memory stores/atomics
Fixes: 13ab63bb62b ('radv: Implement VK_EXT_buffer_device_address.')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 35fab1ba3395604f748cd13ba82991372ca0cae7)
Diffstat (limited to 'src/amd/vulkan/radv_shader_info.c')
| -rw-r--r-- | src/amd/vulkan/radv_shader_info.c | 33 |
1 files changed, 25 insertions, 8 deletions
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 60e0cd22fb0..5384d1a0d17 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -152,6 +152,15 @@ set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr, } static void +set_writes_memory(const nir_shader *nir, struct radv_shader_info *info) +{ + if (nir->info.stage == MESA_SHADER_FRAGMENT) + info->ps.writes_memory = true; + else if (nir->info.stage == MESA_SHADER_GEOMETRY) + info->gs.writes_memory = true; +} + +static void gather_intrinsic_store_deref_info(const nir_shader *nir, const nir_intrinsic_instr *instr, struct radv_shader_info *info) @@ -308,10 +317,7 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr, instr->intrinsic == nir_intrinsic_image_deref_atomic_xor || instr->intrinsic == nir_intrinsic_image_deref_atomic_exchange || instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap) { - if (nir->info.stage == MESA_SHADER_FRAGMENT) - info->ps.writes_memory = true; - else if (nir->info.stage == MESA_SHADER_GEOMETRY) - info->gs.writes_memory = true; + set_writes_memory(nir, info); } break; } @@ -326,17 +332,28 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr, case nir_intrinsic_ssbo_atomic_xor: case nir_intrinsic_ssbo_atomic_exchange: case nir_intrinsic_ssbo_atomic_comp_swap: - if (nir->info.stage == MESA_SHADER_FRAGMENT) - info->ps.writes_memory = true; - else if (nir->info.stage == MESA_SHADER_GEOMETRY) - info->gs.writes_memory = true; + set_writes_memory(nir, info); break; case nir_intrinsic_load_deref: gather_intrinsic_load_deref_info(nir, instr, info); break; case nir_intrinsic_store_deref: gather_intrinsic_store_deref_info(nir, instr, info); + /* fallthrough */ + case nir_intrinsic_deref_atomic_add: + case nir_intrinsic_deref_atomic_imin: + case nir_intrinsic_deref_atomic_umin: + case nir_intrinsic_deref_atomic_imax: + case nir_intrinsic_deref_atomic_umax: + case nir_intrinsic_deref_atomic_and: + case nir_intrinsic_deref_atomic_or: + case nir_intrinsic_deref_atomic_xor: + case nir_intrinsic_deref_atomic_exchange: + case nir_intrinsic_deref_atomic_comp_swap: { + if (nir_src_as_deref(instr->src[0])->mode & (nir_var_mem_global | nir_var_mem_ssbo)) + set_writes_memory(nir, info); break; + } default: break; } |