ac,amd/llvm,radv: Initialize structs with {0}

Necessary to compile with MSVC.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7123>

4 files changed, 14 insertions, 14 deletions

diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index bbaed82c492..246a89ee86a 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -573,7 +573,7 @@ void ac_parse_ib_chunk(FILE *f, uint32_t *ib_ptr, int num_dw, const int *trace_i
                        unsigned trace_id_count, enum chip_class chip_class,
                        ac_debug_addr_callback addr_callback, void *addr_callback_data)
 {
-   struct ac_ib_parser ib = {};
+   struct ac_ib_parser ib = {0};
    ib.ib = ib_ptr;
    ib.num_dw = num_dw;
    ib.trace_ids = trace_ids;
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 40db254e556..27b2c52f3a1 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -178,12 +178,12 @@ has_tmz_support(amdgpu_device_handle dev,
 bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
                        struct amdgpu_gpu_info *amdinfo)
 {
-   struct drm_amdgpu_info_device device_info = {};
-   struct amdgpu_buffer_size_alignments alignment_info = {};
-   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
-   struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
-   struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
-   struct amdgpu_gds_resource_info gds = {};
+   struct drm_amdgpu_info_device device_info = {0};
+   struct amdgpu_buffer_size_alignments alignment_info = {0};
+   struct drm_amdgpu_info_hw_ip dma = {0}, compute = {0}, uvd = {0};
+   struct drm_amdgpu_info_hw_ip uvd_enc = {0}, vce = {0}, vcn_dec = {0}, vcn_jpeg = {0};
+   struct drm_amdgpu_info_hw_ip vcn_enc = {0}, gfx = {0};
+   struct amdgpu_gds_resource_info gds = {0};
    uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
    int r, i, j;
    amdgpu_device_handle dev = dev_p;
@@ -331,7 +331,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
    }
 
    if (info->drm_minor >= 9) {
-      struct drm_amdgpu_memory_info meminfo = {};
+      struct drm_amdgpu_memory_info meminfo = {0};
 
       r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
       if (r) {
diff --git a/src/amd/common/ac_rtld.c b/src/amd/common/ac_rtld.c
index 8a9cd7c7a6e..4b54da4b246 100644
--- a/src/amd/common/ac_rtld.c
+++ b/src/amd/common/ac_rtld.c
@@ -202,7 +202,7 @@ static bool read_private_lds_symbols(struct ac_rtld_binary *binary, unsigned par
    size_t num_symbols = symbols_data->d_size / sizeof(Elf64_Sym);
 
    for (size_t j = 0; j < num_symbols; ++j, ++symbol) {
-      struct ac_rtld_symbol s = {};
+      struct ac_rtld_symbol s = {0};
 
       if (ELF64_ST_TYPE(symbol->st_info) == STT_AMDGPU_LDS) {
          /* old-style LDS symbols from initial prototype -- remove eventually */
@@ -520,7 +520,7 @@ bool ac_rtld_read_config(const struct radeon_info *info, struct ac_rtld_binary *
          return false;
 
       /* TODO: be precise about scratch use? */
-      struct ac_shader_config c = {};
+      struct ac_shader_config c = {0};
       ac_parse_shader_binary_config(config_data, config_nbytes, binary->wave_size, true, info, &c);
 
       config->num_sgprs = MAX2(config->num_sgprs, c.num_sgprs);
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 10648d1324e..9eddd3cb7c2 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -185,7 +185,7 @@ ac_compute_dcc_retile_tile_indices(struct ac_addrlib *addrlib, const struct rade
    if (!indices)
       return NULL;
 
-   ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
+   ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {0};
    addrout.size = sizeof(addrout);
 
    for (unsigned y = 0; y < h; ++y) {
@@ -1118,7 +1118,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
        !(surf->flags & RADEON_SURF_NO_FMASK)) {
       ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
       ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
-      ADDR_TILEINFO fmask_tile_info = {};
+      ADDR_TILEINFO fmask_tile_info = {0};
 
       fin.size = sizeof(fin);
       fout.size = sizeof(fout);
@@ -1365,7 +1365,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
                                 const struct ac_surf_config *config, struct radeon_surf *surf,
                                 bool compressed, ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
 {
-   ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
+   ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {0};
    ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
    ADDR_E_RETURNCODE ret;
 
@@ -1500,7 +1500,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
                                    !in->flags.metaPipeUnaligned))) {
          ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
          ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
-         ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
+         ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0};
 
          din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
          dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);