diff options
| author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2020-11-13 17:16:26 +0100 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2020-11-14 12:38:51 +0000 |
| commit | f7b122728d5e015bbd706505e60600a864b43ea7 (patch) | |
| tree | 3c88ed633ded9088d92a85e0e2d575675171ff95 /include | |
| parent | f0c8645cb93bfb29771606b9a6aca4aa1a06d30e (diff) | |
drm/uapi: Fix modifier field mask for AMD modifiers.
The DCC_MAX_COMPRESSED_BLOCK has to contain one of
AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't
fit in 1 bit.
Fix this cleanly while it is only in drm-next.
Fixes: 2cc2b456889 "drm-uapi: Add AMD modifiers."
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7607>
Diffstat (limited to 'include')
| -rw-r--r-- | include/drm-uapi/drm_fourcc.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h index aa89040e7e2..3f9c8110355 100644 --- a/include/drm-uapi/drm_fourcc.h +++ b/include/drm-uapi/drm_fourcc.h @@ -1130,7 +1130,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 -#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* * DCC supports embedding some clear colors directly in the DCC surface. @@ -1141,7 +1141,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * If this bit is set that means the fastclear eliminate is not needed for these * embeddable colors. */ -#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19 +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 /* @@ -1154,15 +1154,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * RB = only for TILE_VER_GFX9 & DCC * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) */ -#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20 +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 -#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23 +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 -#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */ +#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */ #define AMD_FMT_MOD_PACKERS_MASK 0x7 -#define AMD_FMT_MOD_RB_SHIFT 29 +#define AMD_FMT_MOD_RB_SHIFT 30 #define AMD_FMT_MOD_RB_MASK 0x7 -#define AMD_FMT_MOD_PIPE_SHIFT 32 +#define AMD_FMT_MOD_PIPE_SHIFT 33 #define AMD_FMT_MOD_PIPE_MASK 0x7 #define AMD_FMT_MOD_SET(field, value) \ |