compiler: Use util/bitset.h for system_values_read

It is currently a bitset on top of a uint64_t but there are already
more than 64 values.  Change to use BITSET to cover all the
SYSTEM_VALUE_MAX bits.

Backported from 9f3d5e99ea6 ("compiler: Use util/bitset.h for
system_values_read").

Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8728>

25 files changed, 186 insertions, 213 deletions

diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c
index 0a961cb41d1..adddadfdb70 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -1620,14 +1620,16 @@ ntq_setup_vs_inputs(struct v3d_compile *c)
 
         unsigned num_components = 0;
         uint32_t vpm_components_queued = 0;
-        bool uses_iid = c->s->info.system_values_read &
-                (1ull << SYSTEM_VALUE_INSTANCE_ID |
-                 1ull << SYSTEM_VALUE_INSTANCE_INDEX);
-        bool uses_biid = c->s->info.system_values_read &
-                (1ull << SYSTEM_VALUE_BASE_INSTANCE);
-        bool uses_vid = c->s->info.system_values_read &
-                (1ull << SYSTEM_VALUE_VERTEX_ID |
-                 1ull << SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
+        bool uses_iid = BITSET_TEST(c->s->info.system_values_read,
+                                    SYSTEM_VALUE_INSTANCE_ID) ||
+                        BITSET_TEST(c->s->info.system_values_read,
+                                    SYSTEM_VALUE_INSTANCE_INDEX);
+        bool uses_biid = BITSET_TEST(c->s->info.system_values_read,
+                                     SYSTEM_VALUE_BASE_INSTANCE);
+        bool uses_vid = BITSET_TEST(c->s->info.system_values_read,
+                                    SYSTEM_VALUE_VERTEX_ID) ||
+                        BITSET_TEST(c->s->info.system_values_read,
+                                    SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
 
         num_components += uses_iid;
         num_components += uses_biid;
@@ -2079,16 +2081,16 @@ ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
                 * be slower if the VPM unit is busy with another QPU.
                 */
                int index = 0;
-               if (c->s->info.system_values_read &
-                   (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
+               if (BITSET_TEST(c->s->info.system_values_read,
+                               SYSTEM_VALUE_INSTANCE_ID)) {
                       index++;
                }
-               if (c->s->info.system_values_read &
-                   (1ull << SYSTEM_VALUE_BASE_INSTANCE)) {
+               if (BITSET_TEST(c->s->info.system_values_read,
+                               SYSTEM_VALUE_BASE_INSTANCE)) {
                       index++;
                }
-               if (c->s->info.system_values_read &
-                   (1ull << SYSTEM_VALUE_VERTEX_ID)) {
+               if (BITSET_TEST(c->s->info.system_values_read,
+                               SYSTEM_VALUE_VERTEX_ID)) {
                       index++;
                }
                for (int i = 0; i < offset; i++)
@@ -3129,16 +3131,18 @@ nir_to_vir(struct v3d_compile *c)
                         c->uses_implicit_point_line_varyings = true;
                 } else if (c->fs_key->is_lines &&
                            (c->devinfo->ver < 40 ||
-                            (c->s->info.system_values_read &
-                             BITFIELD64_BIT(SYSTEM_VALUE_LINE_COORD)))) {
+                            BITSET_TEST(c->s->info.system_values_read,
+                                        SYSTEM_VALUE_LINE_COORD))) {
                         c->line_x = emit_fragment_varying(c, NULL, -1, 0, 0);
                         c->uses_implicit_point_line_varyings = true;
                 }
 
                 c->force_per_sample_msaa =
                    c->s->info.fs.uses_sample_qualifier ||
-                   (c->s->info.system_values_read & (SYSTEM_BIT_SAMPLE_ID |
-                                                     SYSTEM_BIT_SAMPLE_POS));
+                   BITSET_TEST(c->s->info.system_values_read,
+                               SYSTEM_VALUE_SAMPLE_ID) ||
+                   BITSET_TEST(c->s->info.system_values_read,
+                               SYSTEM_VALUE_SAMPLE_POS);
                 break;
         case MESA_SHADER_COMPUTE:
                 /* Set up the TSO for barriers, assuming we do some. */
diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c
index 3ce8fe4c35f..e245867b9c3 100644
--- a/src/broadcom/compiler/vir.c
+++ b/src/broadcom/compiler/vir.c
@@ -635,16 +635,18 @@ v3d_vs_set_prog_data(struct v3d_compile *c,
                 prog_data->vpm_input_size += c->vattr_sizes[i];
         }
 
-        prog_data->uses_vid = (c->s->info.system_values_read &
-                               (1ull << SYSTEM_VALUE_VERTEX_ID |
-                                1ull << SYSTEM_VALUE_VERTEX_ID_ZERO_BASE));
+        prog_data->uses_vid = BITSET_TEST(c->s->info.system_values_read,
+                                          SYSTEM_VALUE_VERTEX_ID) ||
+                              BITSET_TEST(c->s->info.system_values_read,
+                                          SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
 
-        prog_data->uses_biid = (c->s->info.system_values_read &
-                                (1ull << SYSTEM_VALUE_BASE_INSTANCE));
+        prog_data->uses_biid = BITSET_TEST(c->s->info.system_values_read,
+                                           SYSTEM_VALUE_BASE_INSTANCE);
 
-        prog_data->uses_iid = (c->s->info.system_values_read &
-                               (1ull << SYSTEM_VALUE_INSTANCE_ID |
-                                1ull << SYSTEM_VALUE_INSTANCE_INDEX));
+        prog_data->uses_iid = BITSET_TEST(c->s->info.system_values_read,
+                                          SYSTEM_VALUE_INSTANCE_ID) ||
+                              BITSET_TEST(c->s->info.system_values_read,
+                                          SYSTEM_VALUE_INSTANCE_INDEX);
 
         if (prog_data->uses_vid)
                 prog_data->vpm_input_size++;
@@ -698,8 +700,8 @@ v3d_gs_set_prog_data(struct v3d_compile *c,
          * it after reading it if necessary, so it doesn't add to the VPM
          * size requirements.
          */
-        prog_data->uses_pid = (c->s->info.system_values_read &
-                               (1ull << SYSTEM_VALUE_PRIMITIVE_ID));
+        prog_data->uses_pid = BITSET_TEST(c->s->info.system_values_read,
+                                          SYSTEM_VALUE_PRIMITIVE_ID);
 
         /* Output segment size is in sectors (8 rows of 32 bits per channel) */
         prog_data->vpm_output_size = align(c->vpm_output_size, 8) / 8;
diff --git a/src/compiler/glsl/ir_set_program_inouts.cpp b/src/compiler/glsl/ir_set_program_inouts.cpp
index a3cb19479b8..9657703ead8 100644
--- a/src/compiler/glsl/ir_set_program_inouts.cpp
+++ b/src/compiler/glsl/ir_set_program_inouts.cpp
@@ -124,7 +124,7 @@ mark(struct gl_program *prog, ir_variable *var, int offset, int len,
             prog->info.fs.uses_sample_qualifier |= var->data.sample;
          }
       } else if (var->data.mode == ir_var_system_value) {
-         prog->info.system_values_read |= bitfield;
+         BITSET_SET(prog->info.system_values_read, idx);
       } else {
          assert(var->data.mode == ir_var_shader_out);
          if (is_patch_generic) {
@@ -432,7 +432,7 @@ do_set_program_inouts(exec_list *instructions, struct gl_program *prog,
    prog->info.outputs_read = 0;
    prog->info.patch_inputs_read = 0;
    prog->info.patch_outputs_written = 0;
-   prog->info.system_values_read = 0;
+   BITSET_ZERO(prog->info.system_values_read);
    if (shader_stage == MESA_SHADER_FRAGMENT) {
       prog->info.fs.uses_sample_qualifier = false;
       prog->info.fs.uses_discard = false;
diff --git a/src/compiler/nir/nir_gather_info.c b/src/compiler/nir/nir_gather_info.c
index 4f763f9029c..6fe8a70be53 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -497,40 +497,40 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
    case nir_intrinsic_load_barycentric_model:
    case nir_intrinsic_load_gs_header_ir3:
    case nir_intrinsic_load_tcs_header_ir3:
-      shader->info.system_values_read |=
-         (1ull << nir_system_value_from_intrinsic(instr->intrinsic));
+      BITSET_SET(shader->info.system_values_read,
+                 nir_system_value_from_intrinsic(instr->intrinsic));
       break;
 
    case nir_intrinsic_load_barycentric_pixel:
       if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
           nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
-         shader->info.system_values_read |=
-            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
+         BITSET_SET(shader->info.system_values_read,
+                    SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
       } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
-         shader->info.system_values_read |=
-            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
+         BITSET_SET(shader->info.system_values_read,
+                    SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
       }
       break;
 
    case nir_intrinsic_load_barycentric_centroid:
       if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
           nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
-         shader->info.system_values_read |=
-            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
+         BITSET_SET(shader->info.system_values_read,
+                    SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
       } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
-         shader->info.system_values_read |=
-            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
+         BITSET_SET(shader->info.system_values_read,
+                    SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
       }
       break;
 
    case nir_intrinsic_load_barycentric_sample:
       if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
           nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
-         shader->info.system_values_read |=
-            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
+         BITSET_SET(shader->info.system_values_read,
+                    SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
       } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
-         shader->info.system_values_read |=
-            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
+         BITSET_SET(shader->info.system_values_read,
+                    SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
       }
       if (shader->info.stage == MESA_SHADER_FRAGMENT)
          shader->info.fs.uses_sample_qualifier = true;
@@ -803,7 +803,7 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
    shader->info.patch_outputs_read = 0;
    shader->info.patch_inputs_read = 0;
    shader->info.patch_outputs_written = 0;
-   shader->info.system_values_read = 0;
+   BITSET_ZERO(shader->info.system_values_read);
    shader->info.inputs_read_indirectly = 0;
    shader->info.outputs_accessed_indirectly = 0;
    shader->info.patch_inputs_read_indirectly = 0;
diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
index c6ea75c9570..c63025d5d9c 100644
--- a/src/compiler/shader_enums.h
+++ b/src/compiler/shader_enums.h
@@ -379,14 +379,6 @@ const char *gl_varying_slot_name(gl_varying_slot slot);
 /*@}*/
 
 /**
- * Bitflags for system values.
- */
-#define SYSTEM_BIT_SAMPLE_ID ((uint64_t)1 << SYSTEM_VALUE_SAMPLE_ID)
-#define SYSTEM_BIT_SAMPLE_POS ((uint64_t)1 << SYSTEM_VALUE_SAMPLE_POS)
-#define SYSTEM_BIT_SAMPLE_MASK_IN ((uint64_t)1 << SYSTEM_VALUE_SAMPLE_MASK_IN)
-#define SYSTEM_BIT_LOCAL_INVOCATION_ID ((uint64_t)1 << SYSTEM_VALUE_LOCAL_INVOCATION_ID)
-
-/**
  * If the gl_register_file is PROGRAM_SYSTEM_VALUE, the register index will be
  * one of these values.  If a NIR variable's mode is nir_var_system_value, it
  * will be one of these values.
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index a992ad5f4f3..944f705877a 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -25,6 +25,7 @@
 #ifndef SHADER_INFO_H
 #define SHADER_INFO_H
 
+#include "util/bitset.h"
 #include "shader_enums.h"
 #include <stdint.h>
 
@@ -141,7 +142,7 @@ typedef struct shader_info {
    /* Which outputs are actually read */
    uint64_t outputs_read;
    /* Which system values are actually read */
-   uint64_t system_values_read;
+   BITSET_DECLARE(system_values_read, SYSTEM_VALUE_MAX);
 
    /* Which patch inputs are actually read */
    uint32_t patch_inputs_read;
diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c
index 58dd275d03b..7ee27b4ced0 100644
--- a/src/gallium/auxiliary/nir/nir_to_tgsi.c
+++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c
@@ -2632,7 +2632,7 @@ nir_to_tgsi(struct nir_shader *s,
        * gl-2.1-polygon-stipple-fs on softpipe.
        */
       if ((s->info.inputs_read & VARYING_BIT_POS) ||
-          (s->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD))) {
+          BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRAG_COORD)) {
          ureg_property(c->ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
                        s->info.fs.origin_upper_left ?
                        TGSI_FS_COORD_ORIGIN_UPPER_LEFT :
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 06f69955311..e11fefd3de0 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -653,8 +653,8 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
          load = nir_swizzle(b, load, SWIZ(X, Y, Z, Z), 4);
 
       src = nir_src_for_ssa(load);
-      b->shader->info.system_values_read |=
-         (1ull << nir_system_value_from_intrinsic(op));
+      BITSET_SET(b->shader->info.system_values_read,
+                 nir_system_value_from_intrinsic(op));
 
       break;
    }
diff --git a/src/gallium/drivers/iris/iris_draw.c b/src/gallium/drivers/iris/iris_draw.c
index fc545eb7d36..b989923a130 100644
--- a/src/gallium/drivers/iris/iris_draw.c
+++ b/src/gallium/drivers/iris/iris_draw.c
@@ -92,7 +92,7 @@ iris_update_draw_info(struct iris_context *ice,
       const struct shader_info *tcs_info =
          iris_get_shader_info(ice, MESA_SHADER_TESS_CTRL);
       if (tcs_info &&
-          tcs_info->system_values_read & (1ull << SYSTEM_VALUE_VERTICES_IN)) {
+          BITSET_TEST(tcs_info->system_values_read, SYSTEM_VALUE_VERTICES_IN)) {
          ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_TCS;
          ice->state.shaders[MESA_SHADER_TESS_CTRL].sysvals_need_upload = true;
       }
diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c
index 971fc80b5ac..ebe6f468470 100644
--- a/src/gallium/drivers/iris/iris_program.c
+++ b/src/gallium/drivers/iris/iris_program.c
@@ -1541,7 +1541,7 @@ iris_update_compiled_tes(struct iris_context *ice)
 
    /* TODO: Could compare and avoid flagging this. */
    const struct shader_info *tes_info = &ish->nir->info;
-   if (tes_info->system_values_read & (1ull << SYSTEM_VALUE_VERTICES_IN)) {
+   if (BITSET_TEST(tes_info->system_values_read, SYSTEM_VALUE_VERTICES_IN)) {
       ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_TES;
       ice->state.shaders[MESA_SHADER_TESS_EVAL].sysvals_need_upload = true;
    }
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index dca45e7b73e..f778ce0376f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
@@ -983,10 +983,8 @@ bool Converter::assignSlots() {
    info_out->numOutputs = 0;
    info_out->numSysVals = 0;
 
-   for (uint8_t i = 0; i < SYSTEM_VALUE_MAX; ++i) {
-      if (!(nir->info.system_values_read & 1ull << i))
-         continue;
-
+   uint8_t i;
+   BITSET_FOREACH_SET(i, nir->info.system_values_read, SYSTEM_VALUE_MAX) {
       info_out->sv[info_out->numSysVals].sn = tgsi_get_sysval_semantic(i);
       info_out->sv[info_out->numSysVals].si = 0;
       info_out->sv[info_out->numSysVals].input = 0; // TODO inferSysValDirection(sn);
@@ -1299,14 +1297,14 @@ Converter::parseNIR()
    case Program::TYPE_FRAGMENT:
       info_out->prop.fp.earlyFragTests = nir->info.fs.early_fragment_tests;
       prog->persampleInvocation =
-         (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_ID) ||
-         (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
+         BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
+         BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS);
       info_out->prop.fp.postDepthCoverage = nir->info.fs.post_depth_coverage;
       info_out->prop.fp.readsSampleLocations =
-         (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
+         BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS);
       info_out->prop.fp.usesDiscard = nir->info.fs.uses_discard || nir->info.fs.uses_demote;
       info_out->prop.fp.usesSampleMaskIn =
-         !!(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN);
+         !BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
       break;
    case Program::TYPE_GEOMETRY:
       info_out->prop.gp.instanceCount = nir->info.gs.invocations;
@@ -1327,9 +1325,9 @@ Converter::parseNIR()
       break;
    case Program::TYPE_VERTEX:
       info_out->prop.vp.usesDrawParameters =
-         (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) ||
-         (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE)) ||
-         (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID));
+         BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_VERTEX) ||
+         BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE) ||
+         BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
       break;
    default:
       break;
diff --git a/src/gallium/drivers/panfrost/pan_assemble.c b/src/gallium/drivers/panfrost/pan_assemble.c
index b39ebfed2eb..b529a3d8823 100644
--- a/src/gallium/drivers/panfrost/pan_assemble.c
+++ b/src/gallium/drivers/panfrost/pan_assemble.c
@@ -281,8 +281,8 @@ panfrost_shader_compile(struct panfrost_context *ctx,
         state->sysval_count = program->sysval_count;
         memcpy(state->sysval, program->sysvals, sizeof(state->sysval[0]) * state->sysval_count);
 
-        bool vertex_id = s->info.system_values_read & (1 << SYSTEM_VALUE_VERTEX_ID);
-        bool instance_id = s->info.system_values_read & (1 << SYSTEM_VALUE_INSTANCE_ID);
+        bool vertex_id = BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_VERTEX_ID);
+        bool instance_id = BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
 
         state->writes_global = s->info.writes_memory;
 
@@ -340,10 +340,10 @@ panfrost_shader_compile(struct panfrost_context *ctx,
         state->stack_size = program->tls_size;
 
         state->reads_frag_coord = (s->info.inputs_read & (1 << VARYING_SLOT_POS)) ||
-                                  (s->info.system_values_read & (1 << SYSTEM_VALUE_FRAG_COORD));
+                                  BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRAG_COORD);
         state->reads_point_coord = s->info.inputs_read & (1 << VARYING_SLOT_PNTC);
         state->reads_face = (s->info.inputs_read & (1 << VARYING_SLOT_FACE)) ||
-                            (s->info.system_values_read & (1 << SYSTEM_VALUE_FRONT_FACE));
+                            BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
         state->writes_point_size = s->info.outputs_written & (1 << VARYING_SLOT_PSIZ);
 
         if (outputs_written)
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 553661fc960..f17cb91f98d 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -343,26 +343,26 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
       info->tessfactors_are_def_in_all_invocs = ac_are_tessfactors_def_in_all_invocs(nir);
    }
 
-   info->uses_frontface = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_FRONT_FACE);
-   info->uses_instanceid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID);
-   info->uses_invocationid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_INVOCATION_ID);
-   info->uses_grid_size = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_NUM_WORK_GROUPS);
-   info->uses_subgroup_info = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) ||
-                              nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_SUBGROUP_ID) ||
-                              nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_NUM_SUBGROUPS);
-   info->uses_variable_block_size = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_LOCAL_GROUP_SIZE);
-   info->uses_drawid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID);
-   info->uses_primid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_PRIMITIVE_ID) ||
+   info->uses_frontface = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
+   info->uses_instanceid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
+   info->uses_invocationid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INVOCATION_ID);
+   info->uses_grid_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_WORK_GROUPS);
+   info->uses_subgroup_info = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) ||
+                              BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SUBGROUP_ID) ||
+                              BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_SUBGROUPS);
+   info->uses_variable_block_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_GROUP_SIZE);
+   info->uses_drawid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
+   info->uses_primid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
                        nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID;
-   info->reads_samplemask = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_SAMPLE_MASK_IN);
-   info->reads_tess_factors = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER) ||
-                              nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER);
-   info->uses_linear_sample = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
-   info->uses_linear_centroid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
-   info->uses_linear_center = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
-   info->uses_persp_sample = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
-   info->uses_persp_centroid = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
-   info->uses_persp_center = nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
+   info->reads_samplemask = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
+   info->reads_tess_factors = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_INNER) ||
+                              BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_OUTER);
+   info->uses_linear_sample = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
+   info->uses_linear_centroid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
+   info->uses_linear_center = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
+   info->uses_persp_sample = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
+   info->uses_persp_centroid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
+   info->uses_persp_center = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
 
    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
       info->writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH);
diff --git a/src/gallium/frontends/lavapipe/lvp_pipeline.c b/src/gallium/frontends/lavapipe/lvp_pipeline.c
index 89a665d2af9..a9e5fffa149 100644
--- a/src/gallium/frontends/lavapipe/lvp_pipeline.c
+++ b/src/gallium/frontends/lavapipe/lvp_pipeline.c
@@ -768,8 +768,8 @@ lvp_graphics_pipeline_init(struct lvp_pipeline *pipeline,
 
    if (pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]) {
       if (pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.fs.uses_sample_qualifier ||
-          pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.system_values_read & (SYSTEM_BIT_SAMPLE_ID |
-                                                                                   SYSTEM_BIT_SAMPLE_POS))
+          BITSET_TEST(pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
+          BITSET_TEST(pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS))
          pipeline->force_min_sample = true;
    }
    if (pipeline->pipeline_nir[MESA_SHADER_TESS_CTRL]) {
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 1122b1d6b73..1c9e471f5de 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -8365,7 +8365,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
          emit_shader_time_begin();
 
       if (nir->info.inputs_read > 0 ||
-          (nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) ||
+          BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
           (nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) {
          if (devinfo->gen < 6)
             emit_interpolation_setup_gen4();
@@ -8712,7 +8712,7 @@ brw_nir_populate_wm_prog_data(const nir_shader *shader,
                               struct brw_wm_prog_data *prog_data)
 {
    prog_data->uses_src_depth = prog_data->uses_src_w =
-      shader->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_FRAG_COORD);
+      BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_FRAG_COORD);
 
    /* key->alpha_test_func means simulating alpha testing via discards,
     * so the shader definitely kills pixels.
@@ -8728,14 +8728,14 @@ brw_nir_populate_wm_prog_data(const nir_shader *shader,
    prog_data->persample_dispatch =
       key->multisample_fbo &&
       (key->persample_interp ||
-       (shader->info.system_values_read & (SYSTEM_BIT_SAMPLE_ID |
-                                            SYSTEM_BIT_SAMPLE_POS)) ||
+       BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
+       BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) ||
        shader->info.fs.uses_sample_qualifier ||
        shader->info.outputs_read);
 
    if (devinfo->gen >= 6) {
       prog_data->uses_sample_mask =
-         shader->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN;
+         BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
 
       /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
        *
@@ -8747,7 +8747,7 @@ brw_nir_populate_wm_prog_data(const nir_shader *shader,
        * persample dispatch, we hard-code it to 0.5.
        */
       prog_data->uses_pos_offset = prog_data->persample_dispatch &&
-         (shader->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
+         BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS);
    }
 
    prog_data->has_render_target_reads = shader->info.outputs_read != 0ull;
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 8c45f762c13..a36ffa1506d 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -186,11 +186,10 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
     * included here as it lives in its own vec4.
     */
    const bool has_sgvs =
-      nir->info.system_values_read &
-      (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
-       BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
-       BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
-       BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
+      BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FIRST_VERTEX) ||
+      BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE) ||
+      BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) ||
+      BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
 
    const unsigned num_inputs = util_bitcount64(nir->info.inputs_read);
 
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 8b97312ca20..75bdd5934fb 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2874,43 +2874,35 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
    /* gl_VertexID and gl_InstanceID are system values, but arrive via an
     * incoming vertex attribute.  So, add an extra slot.
     */
-   if (nir->info.system_values_read &
-       (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
-        BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
-        BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
-        BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) {
+   if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FIRST_VERTEX) ||
+       BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE) ||
+       BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) ||
+       BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID)) {
       nr_attribute_slots++;
    }
 
    /* gl_DrawID and IsIndexedDraw share its very own vec4 */
-   if (nir->info.system_values_read &
-       (BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID) |
-        BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))) {
+   if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID) ||
+       BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_IS_INDEXED_DRAW)) {
       nr_attribute_slots++;
    }
 
-   if (nir->info.system_values_read &
-       BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))
+   if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_IS_INDEXED_DRAW))
       prog_data->uses_is_indexed_draw = true;
 
-   if (nir->info.system_values_read &
-       BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX))
+   if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FIRST_VERTEX))
       prog_data->uses_firstvertex = true;
 
-   if (nir->info.system_values_read &
-       BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE))
+   if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE))
       prog_data->uses_baseinstance = true;
 
-   if (nir->info.system_values_read &
-       BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE))
+   if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE))
       prog_data->uses_vertexid = true;
 
-   if (nir->info.system_values_read &
-       BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))
+   if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID))
       prog_data->uses_instanceid = true;
 
-   if (nir->info.system_values_read &
-       BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID))
+   if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID))
           prog_data->uses_drawid = true;
 
    /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp
index 3e0aba03083..9f1368bfd96 100644
--- a/src/intel/compiler/brw_vec4_gs_visitor.cpp
+++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp
@@ -623,7 +623,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
       nir->info.clip_distance_array_size;
 
    prog_data->include_primitive_id =
-      (nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID)) != 0;
+      BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
 
    prog_data->invocations = nir->info.gs.invocations;
 
diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp
index 2a4c379d217..83e01bed8e7 100644
--- a/src/intel/compiler/brw_vec4_tcs.cpp
+++ b/src/intel/compiler/brw_vec4_tcs.cpp
@@ -390,7 +390,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
    brw_postprocess_nir(nir, compiler, is_scalar);
 
    bool has_primitive_id =
-      nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID);
+      BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
 
    prog_data->patch_count_threshold = brw::get_patch_count_threshold(key->input_vertices);
 
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index abe8d099a19..58b098a997c 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -332,7 +332,7 @@ emit:
     * BRW_NEW_FRAGMENT_PROGRAM
     */
    if (devinfo->gen == 4 && !devinfo->is_g4x &&
-       (fp->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD))) {
+       BITSET_TEST(fp->info.system_values_read, SYSTEM_VALUE_FRAG_COORD)) {
       BEGIN_BATCH(2);
       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
       OUT_BATCH(0);
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 53baa141920..3f31a471b53 100644
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -885,10 +885,8 @@ setup_registers_and_variables(struct ptn_compile *c)
    }
 
    /* Create system value variables */
-   uint64_t system_values_read = c->prog->info.system_values_read;
-   while (system_values_read) {
-      const int i = u_bit_scan64(&system_values_read);
-
+   int i;
+   BITSET_FOREACH_SET(i, c->prog->info.system_values_read, SYSTEM_VALUE_MAX) {
       nir_variable *var =
          nir_variable_create(shader, nir_var_system_value, glsl_vec4_type(),
                              ralloc_asprintf(shader, "sv_%d", i));
diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c
index e9a2c96bee5..21d020261be 100644
--- a/src/mesa/program/program.c
+++ b/src/mesa/program/program.c
@@ -524,8 +524,8 @@ _mesa_get_min_invocations_per_fragment(struct gl_context *ctx,
        *  forces per-sample shading"
        */
       if (prog->info.fs.uses_sample_qualifier ||
-          (prog->info.system_values_read & (SYSTEM_BIT_SAMPLE_ID |
-                                            SYSTEM_BIT_SAMPLE_POS)))
+          BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
+          BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS))
          return MAX2(_mesa_geometric_samples(ctx->DrawBuffer), 1);
       else if (ctx->Multisample.SampleShading)
          return MAX2(ceilf(ctx->Multisample.MinSampleShadingValue *
diff --git a/src/mesa/program/programopt.c b/src/mesa/program/programopt.c
index a9c0beb31bc..635205311cc 100644
--- a/src/mesa/program/programopt.c
+++ b/src/mesa/program/programopt.c
@@ -597,7 +597,7 @@ _mesa_program_fragment_position_to_sysval(struct gl_program *prog)
       return;
 
    prog->info.inputs_read &= ~BITFIELD64_BIT(VARYING_SLOT_POS);
-   prog->info.system_values_read |= 1 << SYSTEM_VALUE_FRAG_COORD;
+   BITSET_SET(prog->info.system_values_read, SYSTEM_VALUE_FRAG_COORD);
 
    for (i = 0; i < prog->arb.NumInstructions; i++) {
       struct prog_instruction *inst = prog->arb.Instructions + i;
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 3dc685e71f7..6a904e193e3 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -6807,49 +6807,41 @@ st_translate_program(
 
    /* Declare misc input registers
     */
-   {
-      GLbitfield64 sysInputs = proginfo->info.system_values_read;
-
-      for (i = 0; sysInputs; i++) {
-         if (sysInputs & (1ull << i)) {
-            enum tgsi_semantic semName = tgsi_get_sysval_semantic(i);
-
-            t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
-
-            if (semName == TGSI_SEMANTIC_INSTANCEID ||
-                semName == TGSI_SEMANTIC_VERTEXID) {
-               /* From Gallium perspective, these system values are always
-                * integer, and require native integer support.  However, if
-                * native integer is supported on the vertex stage but not the
-                * pixel stage (e.g, i915g + draw), Mesa will generate IR that
-                * assumes these system values are floats. To resolve the
-                * inconsistency, we insert a U2F.
-                */
-               struct st_context *st = st_context(ctx);
-               struct pipe_screen *pscreen = st->pipe->screen;
-               assert(procType == PIPE_SHADER_VERTEX);
-               assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
-               (void) pscreen;
-               if (!ctx->Const.NativeIntegers) {
-                  struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
-                  ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
-                           t->systemValues[i]);
-                  t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
-               }
-            }
-
-            if (procType == PIPE_SHADER_FRAGMENT &&
-                semName == TGSI_SEMANTIC_POSITION)
-               emit_wpos(st_context(ctx), t, proginfo, ureg,
-                         program->wpos_transform_const);
-
-            if (procType == PIPE_SHADER_FRAGMENT &&
-                semName == TGSI_SEMANTIC_SAMPLEPOS)
-               emit_samplepos_adjustment(t, program->wpos_transform_const);
-
-            sysInputs &= ~(1ull << i);
+   BITSET_FOREACH_SET(i, proginfo->info.system_values_read, SYSTEM_VALUE_MAX) {
+      enum tgsi_semantic semName = tgsi_get_sysval_semantic(i);
+
+      t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
+
+      if (semName == TGSI_SEMANTIC_INSTANCEID ||
+          semName == TGSI_SEMANTIC_VERTEXID) {
+         /* From Gallium perspective, these system values are always
+          * integer, and require native integer support.  However, if
+          * native integer is supported on the vertex stage but not the
+          * pixel stage (e.g, i915g + draw), Mesa will generate IR that
+          * assumes these system values are floats. To resolve the
+          * inconsistency, we insert a U2F.
+          */
+         struct st_context *st = st_context(ctx);
+         struct pipe_screen *pscreen = st->pipe->screen;
+         assert(procType == PIPE_SHADER_VERTEX);
+         assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
+         (void) pscreen;
+         if (!ctx->Const.NativeIntegers) {
+            struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
+            ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
+                     t->systemValues[i]);
+            t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
          }
       }
+
+      if (procType == PIPE_SHADER_FRAGMENT &&
+          semName == TGSI_SEMANTIC_POSITION)
+         emit_wpos(st_context(ctx), t, proginfo, ureg,
+                   program->wpos_transform_const);
+
+      if (procType == PIPE_SHADER_FRAGMENT &&
+          semName == TGSI_SEMANTIC_SAMPLEPOS)
+         emit_samplepos_adjustment(t, program->wpos_transform_const);
    }
 
    t->array_sizes = program->array_sizes;
@@ -7152,8 +7144,8 @@ get_mesa_program_tgsi(struct gl_context *ctx,
    /* This must be done before the uniform storage is associated. */
    if (shader->Stage == MESA_SHADER_FRAGMENT &&
        (prog->info.inputs_read & VARYING_BIT_POS ||
-        prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD) ||
-        prog->info.system_values_read & (1ull << SYSTEM_VALUE_SAMPLE_POS))) {
+        BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
+        BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS))) {
       static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
          STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
       };
diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index dca9acb3f31..c867209078d 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -963,42 +963,37 @@ st_translate_mesa_program(struct gl_context *ctx,
 
    /* Declare misc input registers
     */
-   GLbitfield64 sysInputs = program->info.system_values_read;
-   for (i = 0; sysInputs; i++) {
-      if (sysInputs & (1ull << i)) {
-         unsigned semName = tgsi_get_sysval_semantic(i);
-
-         t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
-
-         if (semName == TGSI_SEMANTIC_INSTANCEID ||
-             semName == TGSI_SEMANTIC_VERTEXID) {
-            /* From Gallium perspective, these system values are always
-             * integer, and require native integer support.  However, if
-             * native integer is supported on the vertex stage but not the
-             * pixel stage (e.g, i915g + draw), Mesa will generate IR that
-             * assumes these system values are floats. To resolve the
-             * inconsistency, we insert a U2F.
-             */
-            struct st_context *st = st_context(ctx);
-            struct pipe_screen *pscreen = st->pipe->screen;
-            assert(procType == PIPE_SHADER_VERTEX);
-            assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
-                   PIPE_SHADER_CAP_INTEGERS));
-            (void) pscreen;  /* silence non-debug build warnings */
-            if (!ctx->Const.NativeIntegers) {
-               struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
-               ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
-                        t->systemValues[i]);
-               t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
-            }
+   BITSET_FOREACH_SET (i, program->info.system_values_read, SYSTEM_VALUE_MAX) {
+      unsigned semName = tgsi_get_sysval_semantic(i);
+
+      t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
+
+      if (semName == TGSI_SEMANTIC_INSTANCEID ||
+          semName == TGSI_SEMANTIC_VERTEXID) {
+         /* From Gallium perspective, these system values are always
+          * integer, and require native integer support.  However, if
+          * native integer is supported on the vertex stage but not the
+          * pixel stage (e.g, i915g + draw), Mesa will generate IR that
+          * assumes these system values are floats. To resolve the
+          * inconsistency, we insert a U2F.
+          */
+         struct st_context *st = st_context(ctx);
+         struct pipe_screen *pscreen = st->pipe->screen;
+         assert(procType == PIPE_SHADER_VERTEX);
+         assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
+                                          PIPE_SHADER_CAP_INTEGERS));
+         (void) pscreen;  /* silence non-debug build warnings */
+         if (!ctx->Const.NativeIntegers) {
+            struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
+            ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
+                     t->systemValues[i]);
+            t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
          }
-
-         if (procType == PIPE_SHADER_FRAGMENT &&
-             semName == TGSI_SEMANTIC_POSITION)
-            emit_wpos(st_context(ctx), t, program, ureg);
-
-          sysInputs &= ~(1ull << i);
       }
+
+      if (procType == PIPE_SHADER_FRAGMENT &&
+          semName == TGSI_SEMANTIC_POSITION)
+         emit_wpos(st_context(ctx), t, program, ureg);
    }
 
    if (program->arb.IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {