diff options
| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2023-10-30 14:04:38 +0100 |
|---|---|---|
| committer | Eric Engestrom <eric@engestrom.ch> | 2023-11-01 14:52:55 +0000 |
| commit | 2b66b23045a48cf4f6370db06a60302632f6abac (patch) | |
| tree | 3d57e1ece0af189e814120a5abcff3a7fbebcdc8 | |
| parent | 18397e51adc40a814e945181196c4b5d94f5bb51 (diff) | |
radv: emit COMPUTE_PIPELINESTAT_ENABLE for CS invocations on ACE
This register seems needed to enable compute shader shader invocations
on GFX7. On GFX8+ it's working fine without emitting this register but
I think it doesn't hurt.
This fixes dEQP-VK.query_pool.statistics_query.*_cq on GFX7.
Fixes: a9945216ba2 ("radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25957>
(cherry picked from commit 17daa08dff0cf9479b27ed7402de61336607ec10)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 32 |
2 files changed, 25 insertions, 9 deletions
diff --git a/.pick_status.json b/.pick_status.json index 757fb016ad9..65a1149f5a1 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -64,7 +64,7 @@ "description": "radv: emit COMPUTE_PIPELINESTAT_ENABLE for CS invocations on ACE", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "a9945216ba223d57ade453d5f855edd93dd3b200", "notes": null diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 8fe25db82ae..ecb00d98575 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -1277,11 +1277,19 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level } if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); + if (qf == RADV_QUEUE_GENERAL) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); + } else if (qf == RADV_QUEUE_COMPUTE) { + radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1)); + } } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); + if (qf == RADV_QUEUE_GENERAL) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); + } else if (qf == RADV_QUEUE_COMPUTE) { + radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0)); + } } } @@ -1469,11 +1477,19 @@ si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl); if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); + if (qf == RADV_QUEUE_GENERAL) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); + } else if (qf == RADV_QUEUE_COMPUTE) { + radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1)); + } } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); + if (qf == RADV_QUEUE_GENERAL) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); + } else if (qf == RADV_QUEUE_COMPUTE) { + radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0)); + } } } |