diff options
| author | Rhys Perry <pendingchaos02@gmail.com> | 2020-08-17 11:28:07 +0100 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2020-08-21 12:55:47 -0700 |
| commit | c2a441c6a206d41f598a3c7a64ab90576ae660a7 (patch) | |
| tree | 50d0e1eb8005307e8365c358f63726bbe8dc40b3 | |
| parent | 831473e56e378f985615ecc2683e7cdaf74047c3 (diff) | |
aco: fix non-rtz pack_half_2x16
We were using the wrong conversion opcode. The high bits are also not
zero'd on GFX10, which can cause v_cvt_pk_u16_u32 to clamp.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: df645fa369d ('aco: implement VK_KHR_shader_float_controls')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6346>
(cherry picked from commit 9c1e0d86a813af7609acf42cfe6bec7401d6405f)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 16 |
2 files changed, 12 insertions, 6 deletions
diff --git a/.pick_status.json b/.pick_status.json index b7a38581c4a..8c31c2b3972 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -94,7 +94,7 @@ "description": "aco: fix non-rtz pack_half_2x16", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "df645fa369d12be4d5e0fd9e4f6d4455caf2f4c3" }, diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 766153498f4..49c111012cc 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2831,12 +2831,18 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) Temp src0 = bld.tmp(v1); Temp src1 = bld.tmp(v1); bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src); - if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz) + if (0 && (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)) { bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1); - else - bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst), - bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0), - bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1)); + } else { + src0 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src0); + src1 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src1); + if (ctx->program->chip_class >= GFX10) { + /* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */ + bld.vop3(aco_opcode::v_pack_b32_f16, Definition(dst), src0, src1); + } else { + bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst), src0, src1); + } + } } else { fprintf(stderr, "Unimplemented NIR instr bit size: "); nir_print_instr(&instr->instr, stderr); |