diff options
| author | Ian Romanick <ian.d.romanick@intel.com> | 2022-01-18 16:30:37 -0800 |
|---|---|---|
| committer | Eric Engestrom <eric@engestrom.ch> | 2022-01-26 18:28:30 +0000 |
| commit | 2c51e9667219718f73b19327ebaab260494730b9 (patch) | |
| tree | 2604190c380de3416776e527334b441ba0dc574c | |
| parent | 107c8232e01aaeed531a4249a5a78610d9171f60 (diff) | |
intel/fs: Fix gl_FrontFacing optimization on Gfx12+
It's not obvious why the (gl_FrontFacing ? -1.0 : 1.0) case was handled
different for Gfx12+ than for previous generations, and it's not
correct. It tries to negate the result as an integer, and it does this
before the mask operation that clears the other bits in the value.
When we eventually support dual-SIMD8 dispatch, the other front-facing
bit is in g1.6 at bit 15, so similar code should be possible there.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: c92fb60007f ("intel/fs/gen12: Implement gl_FrontFacing on gen12+.")
Closes: #5876
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14625>
(cherry picked from commit 945fb51fb59d52223b5c0fe90c37d1cba42eb53c)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 11 |
2 files changed, 6 insertions, 7 deletions
diff --git a/.pick_status.json b/.pick_status.json index 6b76341325a..3c2e8e26c43 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1939,7 +1939,7 @@ "description": "intel/fs: Fix gl_FrontFacing optimization on Gfx12+", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "c92fb60007f9c73a4c174f5f4cbce57fbc5118f4" }, diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index d0b50b6386d..7e48e213e8d 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -547,17 +547,16 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr, /* For (gl_FrontFacing ? 1.0 : -1.0), emit: * - * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W + * or(8) tmp.1<2>W g1.1<0,1,0>W 0x00003f80W * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D * - * and negate the result for (gl_FrontFacing ? -1.0 : 1.0). + * and negate g1.1<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0). */ - bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1), - g1, brw_imm_uw(0x3f80)); - if (value1 == -1.0f) - bld.MOV(tmp, negate(tmp)); + g1.negate = true; + bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1), + g1, brw_imm_uw(0x3f80)); } else if (devinfo->ver >= 6) { /* Bit 15 of g0.0 is 0 if the polygon is front facing. */ fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W)); |