diff options
| author | Anuj Phogat <anuj.phogat@gmail.com> | 2020-09-09 11:05:18 -0700 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2020-10-05 11:27:26 -0700 |
| commit | b38d1d1b25ab4853082e24e8e500cfe061ab0fb1 (patch) | |
| tree | a30304caa381388e5f33bf36e74643814f9f2ad3 | |
| parent | 556d6b099ea0ccc1c5e10d288049248fe1e4e163 (diff) | |
intel/gen9: Enable MSC RAW Hazard Avoidance
Workaround # 22011374674
Applied to i965, iris and anv drivers
No performance impact is observed with WA.
Cc: mesa-stable
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 545d852a7a7bc8a509d22096bdb7fb578d4bab65)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 2 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 2 |
5 files changed, 8 insertions, 1 deletions
diff --git a/.pick_status.json b/.pick_status.json index 68902006bee..921cdd55752 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1039,7 +1039,7 @@ "description": "intel/gen9: Enable MSC RAW Hazard Avoidance", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": null }, diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index e494121ef69..1397e06226c 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -944,6 +944,8 @@ iris_init_render_context(struct iris_batch *batch) iris_pack_state(GENX(CACHE_MODE_1), ®_val, reg) { reg.FloatBlendOptimizationEnable = true; reg.FloatBlendOptimizationEnableMask = true; + reg.MSCRAWHazardAvoidanceBit = true; + reg.MSCRAWHazardAvoidanceBitMask = true; reg.PartialResolveDisableInVC = true; reg.PartialResolveDisableInVCMask = true; } diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index a29938e90de..e490c40f07c 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -131,6 +131,8 @@ genX(init_device_state)(struct anv_device *device) anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1), .FloatBlendOptimizationEnable = true, .FloatBlendOptimizationEnableMask = true, + .MSCRAWHazardAvoidanceBit = true, + .MSCRAWHazardAvoidanceBitMask = true, .PartialResolveDisableInVC = true, .PartialResolveDisableInVCMask = true); diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 76ec9a26a27..e52e75f3a9f 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1561,6 +1561,7 @@ enum brw_pixel_shader_coverage_mask_mode { #define GEN7_CACHE_MODE_0 0x7000 #define GEN7_CACHE_MODE_1 0x7004 # define GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) +# define GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT (1 << 9) # define GEN8_HIZ_NP_PMA_FIX_ENABLE (1 << 11) # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13) # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 564ac0e677e..7d0cf96ddfd 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -206,8 +206,10 @@ brw_upload_initial_gpu_state(struct brw_context *brw) */ brw_load_register_imm32(brw, GEN7_CACHE_MODE_1, REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) | + REG_MASK(GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT) | REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) | GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE | + GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT | GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC); } |