diff options
| author | Anuj Phogat <anuj.phogat@gmail.com> | 2017-11-09 11:30:10 -0800 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2017-11-17 22:52:52 +0000 |
| commit | b3bc46f1c74b5d8ed46e827b4d0b2957f0c9d74a (patch) | |
| tree | 0c5e0bca5e02d321f1b7608fbc641e5133adb6ab | |
| parent | bf0c7200bd46618e6bfda3e3e0ea85afb33fa6c0 (diff) | |
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 1dc45d75bb3ff3085f7356b8ec658111529ff76d)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/intel_blit.c
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 15 |
2 files changed, 17 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index c9b2593def5..eec4e726343 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -463,11 +463,14 @@ brw_emit_mi_flush(struct brw_context *brw) const struct gen_device_info *devinfo = &brw->screen->devinfo; if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) { - BEGIN_BATCH_BLT(4); - OUT_BATCH(MI_FLUSH_DW | (4 - 2)); + const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4; + BEGIN_BATCH_BLT(n_dwords); + OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); + if (n_dwords == 5) + OUT_BATCH(0); ADVANCE_BATCH(); } else { int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index b766f19e289..5f25bfaf616 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -102,14 +102,16 @@ set_blitter_tiling(struct brw_context *brw, uint32_t *__map) { const struct gen_device_info *devinfo = &brw->screen->devinfo; - + const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4; assert(devinfo->gen >= 6); /* Idle the blitter before we update how tiling is interpreted. */ - OUT_BATCH(MI_FLUSH_DW | (4 - 2)); + OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); + if (n_dwords == 5) + OUT_BATCH(0); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(BCS_SWCTRL); @@ -121,7 +123,14 @@ set_blitter_tiling(struct brw_context *brw, #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map) #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \ - BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \ + unsigned set_tiling_batch_size = 0; \ + if (dst_y_tiled || src_y_tiled) { \ + if (devinfo->gen >= 8) \ + set_tiling_batch_size = 16; \ + else \ + set_tiling_batch_size = 14; \ + } \ + BEGIN_BATCH_BLT(n + set_tiling_batch_size); \ if (dst_y_tiled || src_y_tiled) \ SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled) |