diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2019-05-10 14:15:53 -0700 |
|---|---|---|
| committer | Juan A. Suarez Romero <jasuarez@igalia.com> | 2019-05-13 10:41:16 +0000 |
| commit | f7c0ca6d38dc23fbc45593072877b2406217987e (patch) | |
| tree | 562d8f7c703a1247446ad298098c94b90ee1fdbf | |
| parent | 38fdfdaff1889fc9f8ac97a268a6eccb343751fc (diff) | |
iris: Use full ways for L3 cache setup on Icelake.
Anuj fixed this in i965 and anv, but the fix never landed in iris.
Fixes tessellation corruption on Icelake. Thanks to Rafael for
bisecting this and tracking it down.
Fixes: d0996d5fab6 iris: Emit default L3 config for the render pipeline
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
(cherry picked from commit 72ccefb5298203c6e1c4b40b60b5dd356900ad47)
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 677fa5aba53..332fda0dbf0 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -631,6 +631,7 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg, * desirable behavior. */ reg.ErrorDetectionBehaviorControl = true; + reg.UseFullWays = true; #endif reg.URBAllocation = cfg->n[GEN_L3P_URB]; reg.ROAllocation = cfg->n[GEN_L3P_RO]; |