summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorIan Romanick <ian.d.romanick@intel.com>2019-02-27 15:53:55 -0800
committerDylan Baker <dylan@pnwbakers.com>2019-03-07 09:09:26 -0800
commit4621c21d54e777ca6a35893ce73c97b3ce00c9f5 (patch)
tree39b6ece8708fdb14d392c49e30f237702d30afee
parent1cae37f6d3e31ac12914d10b62d62c4ddc89611c (diff)
intel/fs: Fix extract_u8 of an odd byte from a 64-bit integer
In the old code, we would generate the exact same instruction for extract_u8(some_u64, 0) and extract_u8(some_u64, 1). The mask-a-word trick only works for even numbered bytes. This fixes the (new) piglit test tests/spec/arb_gpu_shader_int64/execution/fs-ushr-and-mask.shader_test. v2: Use a SHR instead of an AND. This saves an instruction compared to using two moves. Suggested by Jason. Fixes: 6ac2d169019 ("i965/fs: Fix extract_i8/u8 to a 64-bit destination") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 55e6454d5e9dae6f8f29992af83f99217446da38)
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 9b5b94650c6..6f0d9731cfe 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1500,6 +1500,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W);
bld.MOV(w_temp, subscript(op[0], type, byte));
bld.MOV(result, w_temp);
+ } else if (byte & 1) {
+ /* Extract the high byte from the word containing the desired byte
+ * offset.
+ */
+ bld.SHR(result,
+ subscript(op[0], BRW_REGISTER_TYPE_UW, byte / 2),
+ brw_imm_uw(8));
} else {
/* Otherwise use an AND with 0xff and a word type */
bld.AND(result,