diff options
| author | Dave Airlie <airlied@redhat.com> | 2014-11-18 10:55:44 +1000 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2014-11-19 00:50:01 +0000 |
| commit | 9bd73a81d978f99a9f954b47a61b8a1152766f4f (patch) | |
| tree | 7d8d0200b364f6745d0f72f6e45fb00f98a9ca3a | |
| parent | c44aa54d2c6a89774e06f13cb46d4afee40c3824 (diff) | |
r600g/cayman: fix texture gather tests
It appears on cayman the TG4 outputs were reordered.
This fixes a lot of piglit tests.
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 27e1e0e7108511b43d0f56f678c7201f39e2acc5)
| -rw-r--r-- | src/gallium/drivers/r600/r600_shader.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index b4673f39bb4..33c37a539bc 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -5348,11 +5348,18 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX]; tex.inst_mod = texture_component_select; + if (ctx->bc->chip_class == CAYMAN) { /* GATHER4 result order is different from TGSI TG4 */ - tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; - tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; - tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; - tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; + tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7; + tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7; + tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7; + tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; + } else { + tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; + tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; + tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; + tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; + } } else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) { tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; |