intel/brw: Combine a1/a16 3src type decoding functions

Align16 is only used on Gfx9, while Align1 is used on Gfx11+.  We can
decode both kinds of encodings in the same function with a simple
devinfo check.  One snag is that the align16 encodings didn't have a
separate exec_type field, but we can just pass 0.

This lets us have a single function named brw_type_decode_for_3src,
which is much less of a mouthful.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>

3 files changed, 19 insertions, 32 deletions

diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index a83e0ad97d1..265779bfbf1 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -394,7 +394,7 @@ brw_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo,       \
                                const brw_inst *inst)                          \
 {                                                                             \
    unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst);       \
-   return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type);                 \
+   return brw_type_decode_for_3src(devinfo, hw_type, 0);                      \
 }
 
 REG_TYPE(dst)
@@ -467,7 +467,7 @@ brw_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo,        \
       (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo,  \
                                                                     inst);    \
    unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst);        \
-   return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type);       \
+   return brw_type_decode_for_3src(devinfo, hw_type, exec_type);              \
 }
 
 REG_TYPE(dst)
@@ -577,7 +577,7 @@ brw_inst_dpas_3src_##reg##_type(const struct intel_device_info *devinfo,      \
       (enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\
                                                                       inst);  \
    unsigned hw_type = brw_inst_dpas_3src_##reg##_hw_type(devinfo, inst);      \
-   return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type);       \
+   return brw_type_decode_for_3src(devinfo, hw_type, exec_type);              \
 }
 
 REG_TYPE(dst)
diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c
index aa86787e973..68ec7a000dc 100644
--- a/src/intel/compiler/brw_reg_type.c
+++ b/src/intel/compiler/brw_reg_type.c
@@ -224,30 +224,11 @@ brw_type_encode_for_3src(const struct intel_device_info *devinfo,
 }
 
 /**
- * Convert the hardware representation for a 3-src align16 instruction into a
- * brw_reg_type enumeration value.
+ * Convert the hardware encoding for a 3-src instruction into a brw_reg_type.
  */
 enum brw_reg_type
-brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
-                                 unsigned hw_type)
-{
-   static const enum brw_reg_type tbl[] = {
-      [0] = BRW_TYPE_F,
-      [1] = BRW_TYPE_D,
-      [2] = BRW_TYPE_UD,
-      [3] = BRW_TYPE_DF,
-      [4] = BRW_TYPE_HF,
-   };
-   return hw_type < ARRAY_SIZE(tbl) ? tbl[hw_type] : BRW_TYPE_INVALID;
-}
-
-/**
- * Convert the hardware representation for a 3-src align1 instruction into a
- * brw_reg_type enumeration value.
- */
-enum brw_reg_type
-brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
-                                unsigned hw_type, unsigned exec_type)
+brw_type_decode_for_3src(const struct intel_device_info *devinfo,
+                         unsigned hw_type, unsigned exec_type)
 {
    STATIC_ASSERT(BRW_ALIGN1_3SRC_EXEC_TYPE_INT == 0);
    STATIC_ASSERT(BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT == 1);
@@ -262,7 +243,7 @@ brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
             return BRW_TYPE_INVALID;
       }
       return (enum brw_reg_type) (base_field | size_field);
-   } else {
+   } else if (devinfo->ver >= 11) {
       if (exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT) {
          return hw_type > 1 ? BRW_TYPE_INVALID :
                 hw_type ? BRW_TYPE_F : BRW_TYPE_HF;
@@ -271,6 +252,16 @@ brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
       unsigned size_field = 2 >> (hw_type >> 1);
       unsigned base_field = (hw_type & 1) << 2;
       return (enum brw_reg_type) (base_field | size_field);
+   } else {
+      /* align16 encodings */
+      static const enum brw_reg_type tbl[] = {
+         [0] = BRW_TYPE_F,
+         [1] = BRW_TYPE_D,
+         [2] = BRW_TYPE_UD,
+         [3] = BRW_TYPE_DF,
+         [4] = BRW_TYPE_HF,
+      };
+      return hw_type < ARRAY_SIZE(tbl) ? tbl[hw_type] : BRW_TYPE_INVALID;
    }
 }
 
diff --git a/src/intel/compiler/brw_reg_type.h b/src/intel/compiler/brw_reg_type.h
index d7f7adce72b..771ae5357aa 100644
--- a/src/intel/compiler/brw_reg_type.h
+++ b/src/intel/compiler/brw_reg_type.h
@@ -166,12 +166,8 @@ brw_type_encode_for_3src(const struct intel_device_info *devinfo,
                          enum brw_reg_type type);
 
 enum brw_reg_type
-brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
-                                 unsigned hw_type);
-
-enum brw_reg_type
-brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
-                                unsigned hw_type, unsigned exec_type);
+brw_type_decode_for_3src(const struct intel_device_info *devinfo,
+                         unsigned hw_type, unsigned exec_type);
 
 const char *
 brw_reg_type_to_letters(enum brw_reg_type type);