diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2020-04-22 18:51:42 -0400 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2020-04-29 14:53:25 +0000 |
| commit | e2fbba7720a9bcafc8ca1169697e1b985e84e6f1 (patch) | |
| tree | 3b16799f89df5664a086faba5cf62497a37bd3ca | |
| parent | a3dc7fffbb7be0f1b2ac478b16d3acc5662dff66 (diff) | |
ac/surface: move non-displayable DCC to the end of the buffer
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
| -rw-r--r-- | src/amd/common/ac_surface.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 3b0955dc456..8773fd51b47 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1758,9 +1758,9 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, if (surf->dcc_size && /* dcc_size is computed on GFX9+ only if it's displayable. */ (info->chip_class >= GFX9 || !get_display_flag(config, surf))) { - surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment); - surf->total_size = surf->dcc_offset + surf->dcc_size; - + /* It's better when displayable DCC is immediately after + * the image due to hw-specific reasons. + */ if (info->chip_class >= GFX9 && surf->u.gfx9.dcc_retile_num_elements) { /* Add space for the displayable DCC buffer. */ @@ -1781,6 +1781,9 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, surf->u.gfx9.dcc_retile_num_elements * 4; } } + + surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment); + surf->total_size = surf->dcc_offset + surf->dcc_size; } return 0; |