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authorKamil Horák - 2N <kamilh@axis.com>2025-07-08 11:01:37 +0200
committerJakub Kicinski <kuba@kernel.org>2025-07-09 19:32:30 -0700
commit67c0170566b55b1f6ee3567c94ff679104277e2d (patch)
tree10e7db8077758d6c7e7c5ea08a243b7122b1b427 /Documentation/networking
parent6dfcbd7d1d657994a57b53ad4be834eb783f32bc (diff)
net: phy: MII-Lite PHY interface mode
Some Broadcom PHYs are capable to operate in simplified MII mode, without TXER, RXER, CRS and COL signals as defined for the MII. The MII-Lite mode can be used on most Ethernet controllers with full MII interface by just leaving the input signals (RXER, CRS, COL) inactive. The absence of COL signal makes half-duplex link modes impossible but does not interfere with BroadR-Reach link modes on Broadcom PHYs, because they are all full-duplex only. Add MII-Lite interface mode, especially for Broadcom two-wire PHYs. Signed-off-by: Kamil Horák - 2N <kamilh@axis.com> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/20250708090140.61355-2-kamilh@axis.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'Documentation/networking')
-rw-r--r--Documentation/networking/phy.rst7
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst
index f64641417c54..7f159043ad5a 100644
--- a/Documentation/networking/phy.rst
+++ b/Documentation/networking/phy.rst
@@ -333,6 +333,13 @@ Some of the interface modes are described below:
SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved
through symbol replication. The PCS expects the standard USXGMII code word.
+``PHY_INTERFACE_MODE_MIILITE``
+ Non-standard, simplified MII mode, without TXER, RXER, CRS and COL signals
+ as defined for the MII. The absence of COL signal makes half-duplex link
+ modes impossible but does not interfere with BroadR-Reach link modes on
+ Broadcom (and other two-wire Ethernet) PHYs, because they are full-duplex
+ only.
+
Pause frames / flow control
===========================