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| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2025-09-24 16:40:46 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2025-09-24 16:40:46 +0530 |
| commit | 0d846b42e43351968cdca3b1b65db90997460983 (patch) | |
| tree | dc77e977b89bc220a26b7f896654daeab3a2d136 | |
| parent | 5688b148246672f30532d1d5801119804cb88f97 (diff) | |
| parent | 6916e5fb25c414cb3d4adcfc8f12f55f602c53b2 (diff) | |
Merge remote-tracking branch 'drm-xe/topic/xe-for-CI' into drm-tip
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pci.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pm.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_uc_fw.c | 1 |
3 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 67c808bb22a8..3f42b91efa28 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -371,6 +371,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), + INTEL_PVC_IDS(INTEL_VGA_DEVICE, &pvc_desc), INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index 96afa49f0b4b..b7e3094f8acf 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -357,10 +357,6 @@ ALLOW_ERROR_INJECTION(xe_pm_init_early, ERRNO); /* See xe_pci_probe() */ static u32 vram_threshold_value(struct xe_device *xe) { - /* FIXME: D3Cold temporarily disabled by default on BMG */ - if (xe->info.platform == XE_BATTLEMAGE) - return 0; - return DEFAULT_VRAM_THRESHOLD; } diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c index 622b76078567..6056ecd0b92f 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.c +++ b/drivers/gpu/drm/xe/xe_uc_fw.c @@ -119,6 +119,7 @@ struct fw_blobs_by_type { fw_def(BATTLEMAGE, GT_TYPE_ANY, major_ver(xe, guc, bmg, 70, 49, 4)) \ fw_def(LUNARLAKE, GT_TYPE_ANY, major_ver(xe, guc, lnl, 70, 45, 2)) \ fw_def(METEORLAKE, GT_TYPE_ANY, major_ver(i915, guc, mtl, 70, 44, 1)) \ + fw_def(PVC, GT_TYPE_ANY, mmp_ver(xe, guc, pvc, 70, 44, 1)) \ fw_def(DG2, GT_TYPE_ANY, major_ver(i915, guc, dg2, 70, 45, 2)) \ fw_def(DG1, GT_TYPE_ANY, major_ver(i915, guc, dg1, 70, 44, 1)) \ fw_def(ALDERLAKE_N, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1)) \ |