diff options
Diffstat (limited to 'drivers/iio/adc')
44 files changed, 2620 insertions, 1084 deletions
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index af168e1c9fdb..8bf5b62a73f4 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -354,7 +354,7 @@ config BCM_IPROC_ADC config BERLIN2_ADC tristate "Marvell Berlin2 ADC driver" - depends on ARCH_BERLIN + depends on ARCH_BERLIN || COMPILE_TEST help Marvell Berlin2 ADC driver. This ADC has 8 channels, with one used for temperature measurement. @@ -430,9 +430,9 @@ config EXYNOS_ADC depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 || (OF && COMPILE_TEST) depends on HAS_IOMEM help - Core support for the ADC block found in the Samsung EXYNOS series - of SoCs for drivers such as the touchscreen and hwmon to use to share - this resource. + Driver for the ADC block found in the Samsung S3C (S3C2410, S3C2416, + S3C2440, S3C2443, S3C6410), S5Pv210 and Exynos SoCs. + Choose Y here only if you build for such Samsung SoC. To compile this driver as a module, choose M here: the module will be called exynos_adc. @@ -530,6 +530,16 @@ config IMX7D_ADC This driver can also be built as a module. If so, the module will be called imx7d_adc. +config IMX8QXP_ADC + tristate "NXP IMX8QXP ADC driver" + depends on ARCH_MXC_ARM64 || COMPILE_TEST + depends on HAS_IOMEM + help + Say yes here to build support for IMX8QXP ADC. + + This driver can also be built as a module. If so, the module will be + called imx8qxp-adc. + config LP8788_ADC tristate "LP8788 ADC driver" depends on MFD_LP8788 diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index d68550f493e3..d3f53549720c 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_FSL_MX25_ADC) += fsl-imx25-gcq.o obj-$(CONFIG_HI8435) += hi8435.o obj-$(CONFIG_HX711) += hx711.o obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o +obj-$(CONFIG_IMX8QXP_ADC) += imx8qxp-adc.o obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o obj-$(CONFIG_INGENIC_ADC) += ingenic-adc.o obj-$(CONFIG_INTEL_MRFLD_ADC) += intel_mrfld_adc.o diff --git a/drivers/iio/adc/ab8500-gpadc.c b/drivers/iio/adc/ab8500-gpadc.c index 7b5212ba5501..4c46a201d4ef 100644 --- a/drivers/iio/adc/ab8500-gpadc.c +++ b/drivers/iio/adc/ab8500-gpadc.c @@ -1103,17 +1103,15 @@ static int ab8500_gpadc_probe(struct platform_device *pdev) return ret; gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END"); - if (gpadc->irq_sw < 0) { - dev_err(dev, "failed to get platform sw_conv_end irq\n"); - return gpadc->irq_sw; - } + if (gpadc->irq_sw < 0) + return dev_err_probe(dev, gpadc->irq_sw, + "failed to get platform sw_conv_end irq\n"); if (is_ab8500(gpadc->ab8500)) { gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END"); - if (gpadc->irq_hw < 0) { - dev_err(dev, "failed to get platform hw_conv_end irq\n"); - return gpadc->irq_hw; - } + if (gpadc->irq_hw < 0) + return dev_err_probe(dev, gpadc->irq_hw, + "failed to get platform hw_conv_end irq\n"); } else { gpadc->irq_hw = 0; } @@ -1146,11 +1144,9 @@ static int ab8500_gpadc_probe(struct platform_device *pdev) /* The VTVout LDO used to power the AB8500 GPADC */ gpadc->vddadc = devm_regulator_get(dev, "vddadc"); - if (IS_ERR(gpadc->vddadc)) { - ret = PTR_ERR(gpadc->vddadc); - dev_err(dev, "failed to get vddadc\n"); - return ret; - } + if (IS_ERR(gpadc->vddadc)) + return dev_err_probe(dev, PTR_ERR(gpadc->vddadc), + "failed to get vddadc\n"); ret = regulator_enable(gpadc->vddadc); if (ret) { diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index ee8ed9481025..2121a812b0c3 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -293,6 +293,7 @@ static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { .has_registers = true, .addr_shift = 3, .read_mask = BIT(6), + .irq_flags = IRQF_TRIGGER_FALLING, }; static const struct ad_sd_calib_data ad7192_calib_arr[8] = { diff --git a/drivers/iio/adc/ad7291.c b/drivers/iio/adc/ad7291.c index 2301a0e27f23..e9129dac762f 100644 --- a/drivers/iio/adc/ad7291.c +++ b/drivers/iio/adc/ad7291.c @@ -460,6 +460,11 @@ static const struct iio_info ad7291_info = { .write_event_value = &ad7291_write_event_value, }; +static void ad7291_reg_disable(void *reg) +{ + regulator_disable(reg); +} + static int ad7291_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -473,8 +478,6 @@ static int ad7291_probe(struct i2c_client *client, chip = iio_priv(indio_dev); mutex_init(&chip->state_lock); - /* this is only used for device removal purposes */ - i2c_set_clientdata(client, indio_dev); chip->client = client; @@ -495,6 +498,11 @@ static int ad7291_probe(struct i2c_client *client, if (ret) return ret; + ret = devm_add_action_or_reset(&client->dev, ad7291_reg_disable, + chip->reg); + if (ret) + return ret; + chip->command |= AD7291_EXT_REF; } @@ -506,58 +514,25 @@ static int ad7291_probe(struct i2c_client *client, indio_dev->modes = INDIO_DIRECT_MODE; ret = ad7291_i2c_write(chip, AD7291_COMMAND, AD7291_RESET); - if (ret) { - ret = -EIO; - goto error_disable_reg; - } + if (ret) + return -EIO; ret = ad7291_i2c_write(chip, AD7291_COMMAND, chip->command); - if (ret) { - ret = -EIO; - goto error_disable_reg; - } + if (ret) + return -EIO; if (client->irq > 0) { - ret = request_threaded_irq(client->irq, - NULL, - &ad7291_event_handler, - IRQF_TRIGGER_LOW | IRQF_ONESHOT, - id->name, - indio_dev); + ret = devm_request_threaded_irq(&client->dev, client->irq, + NULL, + &ad7291_event_handler, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, + id->name, + indio_dev); if (ret) - goto error_disable_reg; + return ret; } - ret = iio_device_register(indio_dev); - if (ret) - goto error_unreg_irq; - - return 0; - -error_unreg_irq: - if (client->irq) - free_irq(client->irq, indio_dev); -error_disable_reg: - if (chip->reg) - regulator_disable(chip->reg); - - return ret; -} - -static int ad7291_remove(struct i2c_client *client) -{ - struct iio_dev *indio_dev = i2c_get_clientdata(client); - struct ad7291_chip_info *chip = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - - if (client->irq) - free_irq(client->irq, indio_dev); - - if (chip->reg) - regulator_disable(chip->reg); - - return 0; + return devm_iio_device_register(&client->dev, indio_dev); } static const struct i2c_device_id ad7291_id[] = { @@ -579,7 +554,6 @@ static struct i2c_driver ad7291_driver = { .of_match_table = ad7291_of_match, }, .probe = ad7291_probe, - .remove = ad7291_remove, .id_table = ad7291_id, }; module_i2c_driver(ad7291_driver); diff --git a/drivers/iio/adc/ad7780.c b/drivers/iio/adc/ad7780.c index 42bb952f4738..b6e8c8abf6f4 100644 --- a/drivers/iio/adc/ad7780.c +++ b/drivers/iio/adc/ad7780.c @@ -203,7 +203,7 @@ static const struct ad_sigma_delta_info ad7780_sigma_delta_info = { .set_mode = ad7780_set_mode, .postprocess_sample = ad7780_postprocess_sample, .has_registers = false, - .irq_flags = IRQF_TRIGGER_LOW, + .irq_flags = IRQF_TRIGGER_FALLING, }; #define _AD7780_CHANNEL(_bits, _wordsize, _mask_all) \ diff --git a/drivers/iio/adc/ad7793.c b/drivers/iio/adc/ad7793.c index ef3e2d3ecb0c..0e7ab3fb072a 100644 --- a/drivers/iio/adc/ad7793.c +++ b/drivers/iio/adc/ad7793.c @@ -206,7 +206,7 @@ static const struct ad_sigma_delta_info ad7793_sigma_delta_info = { .has_registers = true, .addr_shift = 3, .read_mask = BIT(6), - .irq_flags = IRQF_TRIGGER_LOW, + .irq_flags = IRQF_TRIGGER_FALLING, }; static const struct ad_sd_calib_data ad7793_calib_arr[6] = { diff --git a/drivers/iio/adc/ad7949.c b/drivers/iio/adc/ad7949.c index 1b4b3203e428..44bb5fde83de 100644 --- a/drivers/iio/adc/ad7949.c +++ b/drivers/iio/adc/ad7949.c @@ -11,12 +11,41 @@ #include <linux/module.h> #include <linux/regulator/consumer.h> #include <linux/spi/spi.h> +#include <linux/bitfield.h> -#define AD7949_MASK_CHANNEL_SEL GENMASK(9, 7) -#define AD7949_MASK_TOTAL GENMASK(13, 0) -#define AD7949_OFFSET_CHANNEL_SEL 7 -#define AD7949_CFG_READ_BACK 0x1 -#define AD7949_CFG_REG_SIZE_BITS 14 +#define AD7949_CFG_MASK_TOTAL GENMASK(13, 0) + +/* CFG: Configuration Update */ +#define AD7949_CFG_MASK_OVERWRITE BIT(13) + +/* INCC: Input Channel Configuration */ +#define AD7949_CFG_MASK_INCC GENMASK(12, 10) +#define AD7949_CFG_VAL_INCC_UNIPOLAR_GND 7 +#define AD7949_CFG_VAL_INCC_UNIPOLAR_COMM 6 +#define AD7949_CFG_VAL_INCC_UNIPOLAR_DIFF 4 +#define AD7949_CFG_VAL_INCC_TEMP 3 +#define AD7949_CFG_VAL_INCC_BIPOLAR 2 +#define AD7949_CFG_VAL_INCC_BIPOLAR_DIFF 0 + +/* INX: Input channel Selection in a binary fashion */ +#define AD7949_CFG_MASK_INX GENMASK(9, 7) + +/* BW: select bandwidth for low-pass filter. Full or Quarter */ +#define AD7949_CFG_MASK_BW_FULL BIT(6) + +/* REF: reference/buffer selection */ +#define AD7949_CFG_MASK_REF GENMASK(5, 3) +#define AD7949_CFG_VAL_REF_EXT_TEMP_BUF 3 +#define AD7949_CFG_VAL_REF_EXT_TEMP 2 +#define AD7949_CFG_VAL_REF_INT_4096 1 +#define AD7949_CFG_VAL_REF_INT_2500 0 +#define AD7949_CFG_VAL_REF_EXTERNAL BIT(1) + +/* SEQ: channel sequencer. Allows for scanning channels */ +#define AD7949_CFG_MASK_SEQ GENMASK(2, 1) + +/* RB: Read back the CFG register */ +#define AD7949_CFG_MASK_RBN BIT(0) enum { ID_AD7949 = 0, @@ -41,41 +70,51 @@ static const struct ad7949_adc_spec ad7949_adc_spec[] = { * @vref: regulator generating Vref * @indio_dev: reference to iio structure * @spi: reference to spi structure + * @refsel: reference selection * @resolution: resolution of the chip * @cfg: copy of the configuration register * @current_channel: current channel in use * @buffer: buffer to send / receive data to / from device + * @buf8b: be16 buffer to exchange data with the device in 8-bit transfers */ struct ad7949_adc_chip { struct mutex lock; struct regulator *vref; struct iio_dev *indio_dev; struct spi_device *spi; + u32 refsel; u8 resolution; u16 cfg; unsigned int current_channel; u16 buffer ____cacheline_aligned; + __be16 buf8b; }; static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val, u16 mask) { int ret; - int bits_per_word = ad7949_adc->resolution; - int shift = bits_per_word - AD7949_CFG_REG_SIZE_BITS; - struct spi_message msg; - struct spi_transfer tx[] = { - { - .tx_buf = &ad7949_adc->buffer, - .len = 2, - .bits_per_word = bits_per_word, - }, - }; ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask); - ad7949_adc->buffer = ad7949_adc->cfg << shift; - spi_message_init_with_transfers(&msg, tx, 1); - ret = spi_sync(ad7949_adc->spi, &msg); + + switch (ad7949_adc->spi->bits_per_word) { + case 16: + ad7949_adc->buffer = ad7949_adc->cfg << 2; + ret = spi_write(ad7949_adc->spi, &ad7949_adc->buffer, 2); + break; + case 14: + ad7949_adc->buffer = ad7949_adc->cfg; + ret = spi_write(ad7949_adc->spi, &ad7949_adc->buffer, 2); + break; + case 8: + /* Here, type is big endian as it must be sent in two transfers */ + ad7949_adc->buf8b = cpu_to_be16(ad7949_adc->cfg << 2); + ret = spi_write(ad7949_adc->spi, &ad7949_adc->buf8b, 2); + break; + default: + dev_err(&ad7949_adc->indio_dev->dev, "unsupported BPW\n"); + return -EINVAL; + } /* * This delay is to avoid a new request before the required time to @@ -90,16 +129,6 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val, { int ret; int i; - int bits_per_word = ad7949_adc->resolution; - int mask = GENMASK(ad7949_adc->resolution - 1, 0); - struct spi_message msg; - struct spi_transfer tx[] = { - { - .rx_buf = &ad7949_adc->buffer, - .len = 2, - .bits_per_word = bits_per_word, - }, - }; /* * 1: write CFG for sample N and read old data (sample N-2) @@ -109,8 +138,8 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val, */ for (i = 0; i < 2; i++) { ret = ad7949_spi_write_cfg(ad7949_adc, - channel << AD7949_OFFSET_CHANNEL_SEL, - AD7949_MASK_CHANNEL_SEL); + FIELD_PREP(AD7949_CFG_MASK_INX, channel), + AD7949_CFG_MASK_INX); if (ret) return ret; if (channel == ad7949_adc->current_channel) @@ -118,9 +147,11 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val, } /* 3: write something and read actual data */ - ad7949_adc->buffer = 0; - spi_message_init_with_transfers(&msg, tx, 1); - ret = spi_sync(ad7949_adc->spi, &msg); + if (ad7949_adc->spi->bits_per_word == 8) + ret = spi_read(ad7949_adc->spi, &ad7949_adc->buf8b, 2); + else + ret = spi_read(ad7949_adc->spi, &ad7949_adc->buffer, 2); + if (ret) return ret; @@ -132,7 +163,25 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val, ad7949_adc->current_channel = channel; - *val = ad7949_adc->buffer & mask; + switch (ad7949_adc->spi->bits_per_word) { + case 16: + *val = ad7949_adc->buffer; + /* Shift-out padding bits */ + *val >>= 16 - ad7949_adc->resolution; + break; + case 14: + *val = ad7949_adc->buffer & GENMASK(13, 0); + break; + case 8: + /* Here, type is big endian as data was sent in two transfers */ + *val = be16_to_cpu(ad7949_adc->buf8b); + /* Shift-out padding bits */ + *val >>= 16 - ad7949_adc->resolution; + break; + default: + dev_err(&ad7949_adc->indio_dev->dev, "unsupported BPW\n"); + return -EINVAL; + } return 0; } @@ -178,12 +227,26 @@ static int ad7949_spi_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - ret = regulator_get_voltage(ad7949_adc->vref); - if (ret < 0) - return ret; + switch (ad7949_adc->refsel) { + case AD7949_CFG_VAL_REF_INT_2500: + *val = 2500; + break; + case AD7949_CFG_VAL_REF_INT_4096: + *val = 4096; + break; + case AD7949_CFG_VAL_REF_EXT_TEMP: + case AD7949_CFG_VAL_REF_EXT_TEMP_BUF: + ret = regulator_get_voltage(ad7949_adc->vref); + if (ret < 0) + return ret; + + /* convert value back to mV */ + *val = ret / 1000; + break; + } - *val = ret / 5000; - return IIO_VAL_INT; + *val2 = (1 << ad7949_adc->resolution) - 1; + return IIO_VAL_FRACTIONAL; } return -EINVAL; @@ -199,8 +262,8 @@ static int ad7949_spi_reg_access(struct iio_dev *indio_dev, if (readval) *readval = ad7949_adc->cfg; else - ret = ad7949_spi_write_cfg(ad7949_adc, - writeval & AD7949_MASK_TOTAL, AD7949_MASK_TOTAL); + ret = ad7949_spi_write_cfg(ad7949_adc, writeval, + AD7949_CFG_MASK_TOTAL); return ret; } @@ -214,10 +277,19 @@ static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc) { int ret; int val; + u16 cfg; - /* Sequencer disabled, CFG readback disabled, IN0 as default channel */ ad7949_adc->current_channel = 0; - ret = ad7949_spi_write_cfg(ad7949_adc, 0x3C79, AD7949_MASK_TOTAL); + + cfg = FIELD_PREP(AD7949_CFG_MASK_OVERWRITE, 1) | + FIELD_PREP(AD7949_CFG_MASK_INCC, AD7949_CFG_VAL_INCC_UNIPOLAR_GND) | + FIELD_PREP(AD7949_CFG_MASK_INX, ad7949_adc->current_channel) | + FIELD_PREP(AD7949_CFG_MASK_BW_FULL, 1) | + FIELD_PREP(AD7949_CFG_MASK_REF, ad7949_adc->refsel) | + FIELD_PREP(AD7949_CFG_MASK_SEQ, 0x0) | + FIELD_PREP(AD7949_CFG_MASK_RBN, 1); + + ret = ad7949_spi_write_cfg(ad7949_adc, cfg, AD7949_CFG_MASK_TOTAL); /* * Do two dummy conversions to apply the first configuration setting. @@ -229,12 +301,19 @@ static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc) return ret; } +static void ad7949_disable_reg(void *reg) +{ + regulator_disable(reg); +} + static int ad7949_spi_probe(struct spi_device *spi) { + u32 spi_ctrl_mask = spi->controller->bits_per_word_mask; struct device *dev = &spi->dev; const struct ad7949_adc_spec *spec; struct ad7949_adc_chip *ad7949_adc; struct iio_dev *indio_dev; + u32 tmp; int ret; indio_dev = devm_iio_device_alloc(dev, sizeof(*ad7949_adc)); @@ -257,16 +336,64 @@ static int ad7949_spi_probe(struct spi_device *spi) indio_dev->num_channels = spec->num_channels; ad7949_adc->resolution = spec->resolution; - ad7949_adc->vref = devm_regulator_get(dev, "vref"); + /* Set SPI bits per word */ + if (spi_ctrl_mask & SPI_BPW_MASK(ad7949_adc->resolution)) { + spi->bits_per_word = ad7949_adc->resolution; + } else if (spi_ctrl_mask == SPI_BPW_MASK(16)) { + spi->bits_per_word = 16; + } else if (spi_ctrl_mask == SPI_BPW_MASK(8)) { + spi->bits_per_word = 8; + } else { + dev_err(dev, "unable to find common BPW with spi controller\n"); + return -EINVAL; + } + + /* Setup internal voltage reference */ + tmp = 4096000; + device_property_read_u32(dev, "adi,internal-ref-microvolt", &tmp); + + switch (tmp) { + case 2500000: + ad7949_adc->refsel = AD7949_CFG_VAL_REF_INT_2500; + break; + case 4096000: + ad7949_adc->refsel = AD7949_CFG_VAL_REF_INT_4096; + break; + default: + dev_err(dev, "unsupported internal voltage reference\n"); + return -EINVAL; + } + + /* Setup external voltage reference, buffered? */ + ad7949_adc->vref = devm_regulator_get_optional(dev, "vrefin"); if (IS_ERR(ad7949_adc->vref)) { - dev_err(dev, "fail to request regulator\n"); - return PTR_ERR(ad7949_adc->vref); + ret = PTR_ERR(ad7949_adc->vref); + if (ret != -ENODEV) + return ret; + /* unbuffered? */ + ad7949_adc->vref = devm_regulator_get_optional(dev, "vref"); + if (IS_ERR(ad7949_adc->vref)) { + ret = PTR_ERR(ad7949_adc->vref); + if (ret != -ENODEV) + return ret; + } else { + ad7949_adc->refsel = AD7949_CFG_VAL_REF_EXT_TEMP; + } + } else { + ad7949_adc->refsel = AD7949_CFG_VAL_REF_EXT_TEMP_BUF; } - ret = regulator_enable(ad7949_adc->vref); - if (ret < 0) { - dev_err(dev, "fail to enable regulator\n"); - return ret; + if (ad7949_adc->refsel & AD7949_CFG_VAL_REF_EXTERNAL) { + ret = regulator_enable(ad7949_adc->vref); + if (ret < 0) { + dev_err(dev, "fail to enable regulator\n"); + return ret; + } + + ret = devm_add_action_or_reset(dev, ad7949_disable_reg, + ad7949_adc->vref); + if (ret) + return ret; } mutex_init(&ad7949_adc->lock); @@ -274,36 +401,16 @@ static int ad7949_spi_probe(struct spi_device *spi) ret = ad7949_spi_init(ad7949_adc); if (ret) { dev_err(dev, "enable to init this device: %d\n", ret); - goto err; + return ret; } - ret = iio_device_register(indio_dev); - if (ret) { + ret = devm_iio_device_register(dev, indio_dev); + if (ret) dev_err(dev, "fail to register iio device: %d\n", ret); - goto err; - } - - return 0; - -err: - mutex_destroy(&ad7949_adc->lock); - regulator_disable(ad7949_adc->vref); return ret; } -static int ad7949_spi_remove(struct spi_device *spi) -{ - struct iio_dev *indio_dev = spi_get_drvdata(spi); - struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - mutex_destroy(&ad7949_adc->lock); - regulator_disable(ad7949_adc->vref); - - return 0; -} - static const struct of_device_id ad7949_spi_of_id[] = { { .compatible = "adi,ad7949" }, { .compatible = "adi,ad7682" }, @@ -326,7 +433,6 @@ static struct spi_driver ad7949_spi_driver = { .of_match_table = ad7949_spi_of_id, }, .probe = ad7949_spi_probe, - .remove = ad7949_spi_remove, .id_table = ad7949_spi_id, }; module_spi_driver(ad7949_spi_driver); diff --git a/drivers/iio/adc/ad799x.c b/drivers/iio/adc/ad799x.c index 18bf8386d50a..220228c375d3 100644 --- a/drivers/iio/adc/ad799x.c +++ b/drivers/iio/adc/ad799x.c @@ -299,7 +299,11 @@ static int ad799x_read_raw(struct iio_dev *indio_dev, GENMASK(chan->scan_type.realbits - 1, 0); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - ret = regulator_get_voltage(st->vref); + if (st->vref) + ret = regulator_get_voltage(st->vref); + else + ret = regulator_get_voltage(st->reg); + if (ret < 0) return ret; *val = ret / 1000; @@ -770,6 +774,7 @@ static int ad799x_probe(struct i2c_client *client, const struct i2c_device_id *id) { int ret; + int extra_config = 0; struct ad799x_state *st; struct iio_dev *indio_dev; const struct ad799x_chip_info *chip_info = @@ -797,14 +802,36 @@ static int ad799x_probe(struct i2c_client *client, ret = regulator_enable(st->reg); if (ret) return ret; - st->vref = devm_regulator_get(&client->dev, "vref"); + + /* check if an external reference is supplied */ + st->vref = devm_regulator_get_optional(&client->dev, "vref"); + if (IS_ERR(st->vref)) { - ret = PTR_ERR(st->vref); - goto error_disable_reg; + if (PTR_ERR(st->vref) == -ENODEV) { + st->vref = NULL; + dev_info(&client->dev, "Using VCC reference voltage\n"); + } else { + ret = PTR_ERR(st->vref); + goto error_disable_reg; + } + } + + if (st->vref) { + /* + * Use external reference voltage if supported by hardware. + * This is optional if voltage / regulator present, use VCC otherwise. + */ + if ((st->id == ad7991) || (st->id == ad7995) || (st->id == ad7999)) { + dev_info(&client->dev, "Using external reference voltage\n"); + extra_config |= AD7991_REF_SEL; + ret = regulator_enable(st->vref); + if (ret) + goto error_disable_reg; + } else { + st->vref = NULL; + dev_warn(&client->dev, "Supplied reference not supported\n"); + } } - ret = regulator_enable(st->vref); - if (ret) - goto error_disable_reg; st->client = client; @@ -815,7 +842,7 @@ static int ad799x_probe(struct i2c_client *client, indio_dev->channels = st->chip_config->channel; indio_dev->num_channels = chip_info->num_channels; - ret = ad799x_update_config(st, st->chip_config->default_config); + ret = ad799x_update_config(st, st->chip_config->default_config | extra_config); if (ret) goto error_disable_vref; @@ -845,7 +872,8 @@ static int ad799x_probe(struct i2c_client *client, error_cleanup_ring: iio_triggered_buffer_cleanup(indio_dev); error_disable_vref: - regulator_disable(st->vref); + if (st->vref) + regulator_disable(st->vref); error_disable_reg: regulator_disable(st->reg); @@ -860,7 +888,8 @@ static int ad799x_remove(struct i2c_client *client) iio_device_unregister(indio_dev); iio_triggered_buffer_cleanup(indio_dev); - regulator_disable(st->vref); + if (st->vref) + regulator_disable(st->vref); regulator_disable(st->reg); kfree(st->rx_buf); @@ -872,7 +901,8 @@ static int __maybe_unused ad799x_suspend(struct device *dev) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); struct ad799x_state *st = iio_priv(indio_dev); - regulator_disable(st->vref); + if (st->vref) + regulator_disable(st->vref); regulator_disable(st->reg); return 0; @@ -889,17 +919,21 @@ static int __maybe_unused ad799x_resume(struct device *dev) dev_err(dev, "Unable to enable vcc regulator\n"); return ret; } - ret = regulator_enable(st->vref); - if (ret) { - regulator_disable(st->reg); - dev_err(dev, "Unable to enable vref regulator\n"); - return ret; + + if (st->vref) { + ret = regulator_enable(st->vref); + if (ret) { + regulator_disable(st->reg); + dev_err(dev, "Unable to enable vref regulator\n"); + return ret; + } } /* resync config */ ret = ad799x_update_config(st, st->config); if (ret) { - regulator_disable(st->vref); + if (st->vref) + regulator_disable(st->vref); regulator_disable(st->reg); return ret; } diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 19efaa41bc34..e939b84cbb56 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -1,8 +1,15 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Aspeed AST2400/2500 ADC + * Aspeed AST2400/2500/2600 ADC * * Copyright (C) 2017 Google, Inc. + * Copyright (C) 2021 Aspeed Technology Inc. + * + * ADC clock formula: + * Ast2400/Ast2500: + * clock period = period of PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0] + 1) + * Ast2600: + * clock period = period of PCLK * 2 * (ADC0C[15:0] + 1) */ #include <linux/clk.h> @@ -13,9 +20,13 @@ #include <linux/module.h> #include <linux/of_platform.h> #include <linux/platform_device.h> +#include <linux/regulator/consumer.h> #include <linux/reset.h> #include <linux/spinlock.h> #include <linux/types.h> +#include <linux/bitfield.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> #include <linux/iio/iio.h> #include <linux/iio/driver.h> @@ -28,34 +39,87 @@ #define ASPEED_REG_INTERRUPT_CONTROL 0x04 #define ASPEED_REG_VGA_DETECT_CONTROL 0x08 #define ASPEED_REG_CLOCK_CONTROL 0x0C -#define ASPEED_REG_MAX 0xC0 - -#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1) -#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1) -#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1) - -#define ASPEED_ENGINE_ENABLE BIT(0) - -#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) +#define ASPEED_REG_COMPENSATION_TRIM 0xC4 +/* + * The register offset between 0xC8~0xCC can be read and won't affect the + * hardware logic in each version of ADC. + */ +#define ASPEED_REG_MAX 0xD0 + +#define ASPEED_ADC_ENGINE_ENABLE BIT(0) +#define ASPEED_ADC_OP_MODE GENMASK(3, 1) +#define ASPEED_ADC_OP_MODE_PWR_DOWN 0 +#define ASPEED_ADC_OP_MODE_STANDBY 1 +#define ASPEED_ADC_OP_MODE_NORMAL 7 +#define ASPEED_ADC_CTRL_COMPENSATION BIT(4) +#define ASPEED_ADC_AUTO_COMPENSATION BIT(5) +/* + * Bit 6 determines not only the reference voltage range but also the dividing + * circuit for battery sensing. + */ +#define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6) +#define ASPEED_ADC_REF_VOLTAGE_2500mV 0 +#define ASPEED_ADC_REF_VOLTAGE_1200mV 1 +#define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2 +#define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3 +#define ASPEED_ADC_BAT_SENSING_DIV BIT(6) +#define ASPEED_ADC_BAT_SENSING_DIV_2_3 0 +#define ASPEED_ADC_BAT_SENSING_DIV_1_3 1 +#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) +#define ASPEED_ADC_CH7_MODE BIT(12) +#define ASPEED_ADC_CH7_NORMAL 0 +#define ASPEED_ADC_CH7_BAT 1 +#define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) +#define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) +#define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch)) #define ASPEED_ADC_INIT_POLLING_TIME 500 #define ASPEED_ADC_INIT_TIMEOUT 500000 +/* + * When the sampling rate is too high, the ADC may not have enough charging + * time, resulting in a low voltage value. Thus, the default uses a slow + * sampling rate for most use cases. + */ +#define ASPEED_ADC_DEF_SAMPLING_RATE 65000 + +struct aspeed_adc_trim_locate { + const unsigned int offset; + const unsigned int field; +}; struct aspeed_adc_model_data { const char *model_name; unsigned int min_sampling_rate; // Hz unsigned int max_sampling_rate; // Hz - unsigned int vref_voltage; // mV + unsigned int vref_fixed_mv; bool wait_init_sequence; + bool need_prescaler; + bool bat_sense_sup; + u8 scaler_bit_width; + unsigned int num_channels; + const struct aspeed_adc_trim_locate *trim_locate; +}; + +struct adc_gain { + u8 mult; + u8 div; }; struct aspeed_adc_data { struct device *dev; + const struct aspeed_adc_model_data *model_data; + struct regulator *regulator; void __iomem *base; spinlock_t clk_lock; + struct clk_hw *fixed_div_clk; struct clk_hw *clk_prescaler; struct clk_hw *clk_scaler; struct reset_control *rst; + int vref_mv; + u32 sample_period_ns; + int cv; + bool battery_sensing; + struct adc_gain battery_mode_gain; }; #define ASPEED_CHAN(_idx, _data_reg_addr) { \ @@ -65,7 +129,8 @@ struct aspeed_adc_data { .address = (_data_reg_addr), \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ - BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ } static const struct iio_chan_spec aspeed_adc_iio_channels[] = { @@ -87,21 +152,170 @@ static const struct iio_chan_spec aspeed_adc_iio_channels[] = { ASPEED_CHAN(15, 0x2E), }; +#define ASPEED_BAT_CHAN(_idx, _data_reg_addr) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = (_idx), \ + .address = (_data_reg_addr), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ +} +static const struct iio_chan_spec aspeed_adc_iio_bat_channels[] = { + ASPEED_CHAN(0, 0x10), + ASPEED_CHAN(1, 0x12), + ASPEED_CHAN(2, 0x14), + ASPEED_CHAN(3, 0x16), + ASPEED_CHAN(4, 0x18), + ASPEED_CHAN(5, 0x1A), + ASPEED_CHAN(6, 0x1C), + ASPEED_BAT_CHAN(7, 0x1E), +}; + +static int aspeed_adc_set_trim_data(struct iio_dev *indio_dev) +{ + struct device_node *syscon; + struct regmap *scu; + u32 scu_otp, trimming_val; + struct aspeed_adc_data *data = iio_priv(indio_dev); + + syscon = of_find_node_by_name(NULL, "syscon"); + if (syscon == NULL) { + dev_warn(data->dev, "Couldn't find syscon node\n"); + return -EOPNOTSUPP; + } + scu = syscon_node_to_regmap(syscon); + if (IS_ERR(scu)) { + dev_warn(data->dev, "Failed to get syscon regmap\n"); + return -EOPNOTSUPP; + } + if (data->model_data->trim_locate) { + if (regmap_read(scu, data->model_data->trim_locate->offset, + &scu_otp)) { + dev_warn(data->dev, + "Failed to get adc trimming data\n"); + trimming_val = 0x8; + } else { + trimming_val = + ((scu_otp) & + (data->model_data->trim_locate->field)) >> + __ffs(data->model_data->trim_locate->field); + } + dev_dbg(data->dev, + "trimming val = %d, offset = %08x, fields = %08x\n", + trimming_val, data->model_data->trim_locate->offset, + data->model_data->trim_locate->field); + writel(trimming_val, data->base + ASPEED_REG_COMPENSATION_TRIM); + } + return 0; +} + +static int aspeed_adc_compensation(struct iio_dev *indio_dev) +{ + struct aspeed_adc_data *data = iio_priv(indio_dev); + u32 index, adc_raw = 0; + u32 adc_engine_control_reg_val; + + adc_engine_control_reg_val = + readl(data->base + ASPEED_REG_ENGINE_CONTROL); + adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE; + adc_engine_control_reg_val |= + (FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | + ASPEED_ADC_ENGINE_ENABLE); + /* + * Enable compensating sensing: + * After that, the input voltage of ADC will force to half of the reference + * voltage. So the expected reading raw data will become half of the max + * value. We can get compensating value = 0x200 - ADC read raw value. + * It is recommended to average at least 10 samples to get a final CV. + */ + writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION | + ASPEED_ADC_CTRL_CHANNEL_ENABLE(0), + data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * After enable compensating sensing mode need to wait some time for ADC stable + * Experiment result is 1ms. + */ + mdelay(1); + + for (index = 0; index < 16; index++) { + /* + * Waiting for the sampling period ensures that the value acquired + * is fresh each time. + */ + ndelay(data->sample_period_ns); + adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address); + } + adc_raw >>= 4; + data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw; + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); + dev_dbg(data->dev, "Compensating value = %d\n", data->cv); + + return 0; +} + +static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate) +{ + struct aspeed_adc_data *data = iio_priv(indio_dev); + + if (rate < data->model_data->min_sampling_rate || + rate > data->model_data->max_sampling_rate) + return -EINVAL; + /* Each sampling needs 12 clocks to convert.*/ + clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE); + rate = clk_get_rate(data->clk_scaler->clk); + data->sample_period_ns = DIV_ROUND_UP_ULL( + (u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate); + dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate, + data->sample_period_ns); + + return 0; +} + static int aspeed_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { struct aspeed_adc_data *data = iio_priv(indio_dev); - const struct aspeed_adc_model_data *model_data = - of_device_get_match_data(data->dev); + u32 adc_engine_control_reg_val; switch (mask) { case IIO_CHAN_INFO_RAW: - *val = readw(data->base + chan->address); + if (data->battery_sensing && chan->channel == 7) { + adc_engine_control_reg_val = + readl(data->base + ASPEED_REG_ENGINE_CONTROL); + writel(adc_engine_control_reg_val | + FIELD_PREP(ASPEED_ADC_CH7_MODE, + ASPEED_ADC_CH7_BAT) | + ASPEED_ADC_BAT_SENSING_ENABLE, + data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * After enable battery sensing mode need to wait some time for adc stable + * Experiment result is 1ms. + */ + mdelay(1); + *val = readw(data->base + chan->address); + *val = (*val * data->battery_mode_gain.mult) / + data->battery_mode_gain.div; + /* Restore control register value */ + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); + } else + *val = readw(data->base + chan->address); + return IIO_VAL_INT; + + case IIO_CHAN_INFO_OFFSET: + if (data->battery_sensing && chan->channel == 7) + *val = (data->cv * data->battery_mode_gain.mult) / + data->battery_mode_gain.div; + else + *val = data->cv; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - *val = model_data->vref_voltage; + *val = data->vref_mv; *val2 = ASPEED_RESOLUTION_BITS; return IIO_VAL_FRACTIONAL_LOG2; @@ -119,19 +333,9 @@ static int aspeed_adc_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { - struct aspeed_adc_data *data = iio_priv(indio_dev); - const struct aspeed_adc_model_data *model_data = - of_device_get_match_data(data->dev); - switch (mask) { case IIO_CHAN_INFO_SAMP_FREQ: - if (val < model_data->min_sampling_rate || - val > model_data->max_sampling_rate) - return -EINVAL; - - clk_set_rate(data->clk_scaler->clk, - val * ASPEED_CLOCKS_PER_SAMPLE); - return 0; + return aspeed_adc_set_sampling_rate(indio_dev, val); case IIO_CHAN_INFO_SCALE: case IIO_CHAN_INFO_RAW: @@ -168,14 +372,119 @@ static const struct iio_info aspeed_adc_iio_info = { .debugfs_reg_access = aspeed_adc_reg_access, }; +static void aspeed_adc_unregister_fixed_divider(void *data) +{ + struct clk_hw *clk = data; + + clk_hw_unregister_fixed_factor(clk); +} + +static void aspeed_adc_reset_assert(void *data) +{ + struct reset_control *rst = data; + + reset_control_assert(rst); +} + +static void aspeed_adc_clk_disable_unprepare(void *data) +{ + struct clk *clk = data; + + clk_disable_unprepare(clk); +} + +static void aspeed_adc_power_down(void *data) +{ + struct aspeed_adc_data *priv_data = data; + + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), + priv_data->base + ASPEED_REG_ENGINE_CONTROL); +} + +static void aspeed_adc_reg_disable(void *data) +{ + struct regulator *reg = data; + + regulator_disable(reg); +} + +static int aspeed_adc_vref_config(struct iio_dev *indio_dev) +{ + struct aspeed_adc_data *data = iio_priv(indio_dev); + int ret; + u32 adc_engine_control_reg_val; + + if (data->model_data->vref_fixed_mv) { + data->vref_mv = data->model_data->vref_fixed_mv; + return 0; + } + adc_engine_control_reg_val = + readl(data->base + ASPEED_REG_ENGINE_CONTROL); + data->regulator = devm_regulator_get_optional(data->dev, "vref"); + if (!IS_ERR(data->regulator)) { + ret = regulator_enable(data->regulator); + if (ret) + return ret; + ret = devm_add_action_or_reset( + data->dev, aspeed_adc_reg_disable, data->regulator); + if (ret) + return ret; + data->vref_mv = regulator_get_voltage(data->regulator); + /* Conversion from uV to mV */ + data->vref_mv /= 1000; + if ((data->vref_mv >= 1550) && (data->vref_mv <= 2700)) + writel(adc_engine_control_reg_val | + FIELD_PREP( + ASPEED_ADC_REF_VOLTAGE, + ASPEED_ADC_REF_VOLTAGE_EXT_HIGH), + data->base + ASPEED_REG_ENGINE_CONTROL); + else if ((data->vref_mv >= 900) && (data->vref_mv <= 1650)) + writel(adc_engine_control_reg_val | + FIELD_PREP( + ASPEED_ADC_REF_VOLTAGE, + ASPEED_ADC_REF_VOLTAGE_EXT_LOW), + data->base + ASPEED_REG_ENGINE_CONTROL); + else { + dev_err(data->dev, "Regulator voltage %d not support", + data->vref_mv); + return -EOPNOTSUPP; + } + } else { + if (PTR_ERR(data->regulator) != -ENODEV) + return PTR_ERR(data->regulator); + data->vref_mv = 2500000; + of_property_read_u32(data->dev->of_node, + "aspeed,int-vref-microvolt", + &data->vref_mv); + /* Conversion from uV to mV */ + data->vref_mv /= 1000; + if (data->vref_mv == 2500) + writel(adc_engine_control_reg_val | + FIELD_PREP(ASPEED_ADC_REF_VOLTAGE, + ASPEED_ADC_REF_VOLTAGE_2500mV), + data->base + ASPEED_REG_ENGINE_CONTROL); + else if (data->vref_mv == 1200) + writel(adc_engine_control_reg_val | + FIELD_PREP(ASPEED_ADC_REF_VOLTAGE, + ASPEED_ADC_REF_VOLTAGE_1200mV), + data->base + ASPEED_REG_ENGINE_CONTROL); + else { + dev_err(data->dev, "Voltage %d not support", data->vref_mv); + return -EOPNOTSUPP; + } + } + + return 0; +} + static int aspeed_adc_probe(struct platform_device *pdev) { struct iio_dev *indio_dev; struct aspeed_adc_data *data; - const struct aspeed_adc_model_data *model_data; - const char *clk_parent_name; int ret; u32 adc_engine_control_reg_val; + unsigned long scaler_flags = 0; + char clk_name[32], clk_parent_name[32]; indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data)); if (!indio_dev) @@ -183,6 +492,8 @@ static int aspeed_adc_probe(struct platform_device *pdev) data = iio_priv(indio_dev); data->dev = &pdev->dev; + data->model_data = of_device_get_match_data(&pdev->dev); + platform_set_drvdata(pdev, indio_dev); data->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(data->base)) @@ -190,45 +501,117 @@ static int aspeed_adc_probe(struct platform_device *pdev) /* Register ADC clock prescaler with source specified by device tree. */ spin_lock_init(&data->clk_lock); - clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0); - - data->clk_prescaler = clk_hw_register_divider( - &pdev->dev, "prescaler", clk_parent_name, 0, - data->base + ASPEED_REG_CLOCK_CONTROL, - 17, 15, 0, &data->clk_lock); - if (IS_ERR(data->clk_prescaler)) - return PTR_ERR(data->clk_prescaler); - + snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s", + of_clk_get_parent_name(pdev->dev.of_node, 0)); + snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div", + data->model_data->model_name); + data->fixed_div_clk = clk_hw_register_fixed_factor( + &pdev->dev, clk_name, clk_parent_name, 0, 1, 2); + if (IS_ERR(data->fixed_div_clk)) + return PTR_ERR(data->fixed_div_clk); + + ret = devm_add_action_or_reset(data->dev, + aspeed_adc_unregister_fixed_divider, + data->fixed_div_clk); + if (ret) + return ret; + snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), clk_name); + + if (data->model_data->need_prescaler) { + snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler", + data->model_data->model_name); + data->clk_prescaler = devm_clk_hw_register_divider( + &pdev->dev, clk_name, clk_parent_name, 0, + data->base + ASPEED_REG_CLOCK_CONTROL, 17, 15, 0, + &data->clk_lock); + if (IS_ERR(data->clk_prescaler)) + return PTR_ERR(data->clk_prescaler); + snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), + clk_name); + scaler_flags = CLK_SET_RATE_PARENT; + } /* * Register ADC clock scaler downstream from the prescaler. Allow rate * setting to adjust the prescaler as well. */ - data->clk_scaler = clk_hw_register_divider( - &pdev->dev, "scaler", "prescaler", - CLK_SET_RATE_PARENT, - data->base + ASPEED_REG_CLOCK_CONTROL, - 0, 10, 0, &data->clk_lock); - if (IS_ERR(data->clk_scaler)) { - ret = PTR_ERR(data->clk_scaler); - goto scaler_error; - } - - data->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); + snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler", + data->model_data->model_name); + data->clk_scaler = devm_clk_hw_register_divider( + &pdev->dev, clk_name, clk_parent_name, scaler_flags, + data->base + ASPEED_REG_CLOCK_CONTROL, 0, + data->model_data->scaler_bit_width, 0, &data->clk_lock); + if (IS_ERR(data->clk_scaler)) + return PTR_ERR(data->clk_scaler); + + data->rst = devm_reset_control_get_shared(&pdev->dev, NULL); if (IS_ERR(data->rst)) { dev_err(&pdev->dev, "invalid or missing reset controller device tree entry"); - ret = PTR_ERR(data->rst); - goto reset_error; + return PTR_ERR(data->rst); } reset_control_deassert(data->rst); - model_data = of_device_get_match_data(&pdev->dev); + ret = devm_add_action_or_reset(data->dev, aspeed_adc_reset_assert, + data->rst); + if (ret) + return ret; - if (model_data->wait_init_sequence) { - /* Enable engine in normal mode. */ - writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE, - data->base + ASPEED_REG_ENGINE_CONTROL); + ret = aspeed_adc_vref_config(indio_dev); + if (ret) + return ret; + if (of_find_property(data->dev->of_node, "aspeed,trim-data-valid", + NULL)) { + ret = aspeed_adc_set_trim_data(indio_dev); + if (ret) + return ret; + } + + if (of_find_property(data->dev->of_node, "aspeed,battery-sensing", + NULL)) { + if (data->model_data->bat_sense_sup) { + data->battery_sensing = 1; + if (readl(data->base + ASPEED_REG_ENGINE_CONTROL) & + ASPEED_ADC_BAT_SENSING_DIV) { + data->battery_mode_gain.mult = 3; + data->battery_mode_gain.div = 1; + } else { + data->battery_mode_gain.mult = 3; + data->battery_mode_gain.div = 2; + } + } else + dev_warn(&pdev->dev, + "Failed to enable battery-sensing mode\n"); + } + + ret = clk_prepare_enable(data->clk_scaler->clk); + if (ret) + return ret; + ret = devm_add_action_or_reset(data->dev, + aspeed_adc_clk_disable_unprepare, + data->clk_scaler->clk); + if (ret) + return ret; + ret = aspeed_adc_set_sampling_rate(indio_dev, + ASPEED_ADC_DEF_SAMPLING_RATE); + if (ret) + return ret; + + adc_engine_control_reg_val = + readl(data->base + ASPEED_REG_ENGINE_CONTROL); + adc_engine_control_reg_val |= + FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | + ASPEED_ADC_ENGINE_ENABLE; + /* Enable engine in normal mode. */ + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); + + ret = devm_add_action_or_reset(data->dev, aspeed_adc_power_down, + data); + if (ret) + return ret; + + if (data->model_data->wait_init_sequence) { /* Wait for initial sequence complete. */ ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL, adc_engine_control_reg_val, @@ -237,87 +620,99 @@ static int aspeed_adc_probe(struct platform_device *pdev) ASPEED_ADC_INIT_POLLING_TIME, ASPEED_ADC_INIT_TIMEOUT); if (ret) - goto poll_timeout_error; + return ret; } + aspeed_adc_compensation(indio_dev); /* Start all channels in normal mode. */ - ret = clk_prepare_enable(data->clk_scaler->clk); - if (ret) - goto clk_enable_error; - - adc_engine_control_reg_val = GENMASK(31, 16) | - ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE; + adc_engine_control_reg_val = + readl(data->base + ASPEED_REG_ENGINE_CONTROL); + adc_engine_control_reg_val |= ASPEED_ADC_CTRL_CHANNEL; writel(adc_engine_control_reg_val, - data->base + ASPEED_REG_ENGINE_CONTROL); + data->base + ASPEED_REG_ENGINE_CONTROL); - model_data = of_device_get_match_data(&pdev->dev); - indio_dev->name = model_data->model_name; + indio_dev->name = data->model_data->model_name; indio_dev->info = &aspeed_adc_iio_info; indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->channels = aspeed_adc_iio_channels; - indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels); - - ret = iio_device_register(indio_dev); - if (ret) - goto iio_register_error; - - return 0; + indio_dev->channels = data->battery_sensing ? + aspeed_adc_iio_bat_channels : + aspeed_adc_iio_channels; + indio_dev->num_channels = data->model_data->num_channels; -iio_register_error: - writel(ASPEED_OPERATION_MODE_POWER_DOWN, - data->base + ASPEED_REG_ENGINE_CONTROL); - clk_disable_unprepare(data->clk_scaler->clk); -clk_enable_error: -poll_timeout_error: - reset_control_assert(data->rst); -reset_error: - clk_hw_unregister_divider(data->clk_scaler); -scaler_error: - clk_hw_unregister_divider(data->clk_prescaler); + ret = devm_iio_device_register(data->dev, indio_dev); return ret; } -static int aspeed_adc_remove(struct platform_device *pdev) -{ - struct iio_dev *indio_dev = platform_get_drvdata(pdev); - struct aspeed_adc_data *data = iio_priv(indio_dev); +static const struct aspeed_adc_trim_locate ast2500_adc_trim = { + .offset = 0x154, + .field = GENMASK(31, 28), +}; - iio_device_unregister(indio_dev); - writel(ASPEED_OPERATION_MODE_POWER_DOWN, - data->base + ASPEED_REG_ENGINE_CONTROL); - clk_disable_unprepare(data->clk_scaler->clk); - reset_control_assert(data->rst); - clk_hw_unregister_divider(data->clk_scaler); - clk_hw_unregister_divider(data->clk_prescaler); +static const struct aspeed_adc_trim_locate ast2600_adc0_trim = { + .offset = 0x5d0, + .field = GENMASK(3, 0), +}; - return 0; -} +static const struct aspeed_adc_trim_locate ast2600_adc1_trim = { + .offset = 0x5d0, + .field = GENMASK(7, 4), +}; static const struct aspeed_adc_model_data ast2400_model_data = { .model_name = "ast2400-adc", - .vref_voltage = 2500, // mV + .vref_fixed_mv = 2500, .min_sampling_rate = 10000, .max_sampling_rate = 500000, + .need_prescaler = true, + .scaler_bit_width = 10, + .num_channels = 16, }; static const struct aspeed_adc_model_data ast2500_model_data = { .model_name = "ast2500-adc", - .vref_voltage = 1800, // mV + .vref_fixed_mv = 1800, .min_sampling_rate = 1, .max_sampling_rate = 1000000, .wait_init_sequence = true, + .need_prescaler = true, + .scaler_bit_width = 10, + .num_channels = 16, + .trim_locate = &ast2500_adc_trim, +}; + +static const struct aspeed_adc_model_data ast2600_adc0_model_data = { + .model_name = "ast2600-adc0", + .min_sampling_rate = 10000, + .max_sampling_rate = 500000, + .wait_init_sequence = true, + .bat_sense_sup = true, + .scaler_bit_width = 16, + .num_channels = 8, + .trim_locate = &ast2600_adc0_trim, +}; + +static const struct aspeed_adc_model_data ast2600_adc1_model_data = { + .model_name = "ast2600-adc1", + .min_sampling_rate = 10000, + .max_sampling_rate = 500000, + .wait_init_sequence = true, + .bat_sense_sup = true, + .scaler_bit_width = 16, + .num_channels = 8, + .trim_locate = &ast2600_adc1_trim, }; static const struct of_device_id aspeed_adc_matches[] = { { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data }, { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data }, + { .compatible = "aspeed,ast2600-adc0", .data = &ast2600_adc0_model_data }, + { .compatible = "aspeed,ast2600-adc1", .data = &ast2600_adc1_model_data }, {}, }; MODULE_DEVICE_TABLE(of, aspeed_adc_matches); static struct platform_driver aspeed_adc_driver = { .probe = aspeed_adc_probe, - .remove = aspeed_adc_remove, .driver = { .name = KBUILD_MODNAME, .of_match_table = aspeed_adc_matches, @@ -327,5 +722,5 @@ static struct platform_driver aspeed_adc_driver = { module_platform_driver(aspeed_adc_driver); MODULE_AUTHOR("Rick Altherr <raltherr@google.com>"); -MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver"); +MODULE_DESCRIPTION("Aspeed AST2400/2500/2600 ADC Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index ea5ca163d879..4c922ef634f8 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -4,6 +4,8 @@ * * Copyright (C) 2015 Atmel, * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> + * 2021 Microchip Technology, Inc. and its subsidiaries + * 2021 Eugen Hristev <eugen.hristev@microchip.com> */ #include <linux/bitops.h> @@ -27,8 +29,9 @@ #include <linux/pinctrl/consumer.h> #include <linux/regulator/consumer.h> +struct at91_adc_reg_layout { /* Control Register */ -#define AT91_SAMA5D2_CR 0x00 + u16 CR; /* Software Reset */ #define AT91_SAMA5D2_CR_SWRST BIT(0) /* Start Conversion */ @@ -39,7 +42,7 @@ #define AT91_SAMA5D2_CR_CMPRST BIT(4) /* Mode Register */ -#define AT91_SAMA5D2_MR 0x04 + u16 MR; /* Trigger Selection */ #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) /* ADTRG */ @@ -82,19 +85,19 @@ #define AT91_SAMA5D2_MR_USEQ BIT(31) /* Channel Sequence Register 1 */ -#define AT91_SAMA5D2_SEQR1 0x08 + u16 SEQR1; /* Channel Sequence Register 2 */ -#define AT91_SAMA5D2_SEQR2 0x0c + u16 SEQR2; /* Channel Enable Register */ -#define AT91_SAMA5D2_CHER 0x10 + u16 CHER; /* Channel Disable Register */ -#define AT91_SAMA5D2_CHDR 0x14 + u16 CHDR; /* Channel Status Register */ -#define AT91_SAMA5D2_CHSR 0x18 + u16 CHSR; /* Last Converted Data Register */ -#define AT91_SAMA5D2_LCDR 0x20 + u16 LCDR; /* Interrupt Enable Register */ -#define AT91_SAMA5D2_IER 0x24 + u16 IER; /* Interrupt Enable Register - TS X measurement ready */ #define AT91_SAMA5D2_IER_XRDY BIT(20) /* Interrupt Enable Register - TS Y measurement ready */ @@ -109,22 +112,31 @@ #define AT91_SAMA5D2_IER_PEN BIT(29) /* Interrupt Enable Register - No pen detect */ #define AT91_SAMA5D2_IER_NOPEN BIT(30) + /* Interrupt Disable Register */ -#define AT91_SAMA5D2_IDR 0x28 + u16 IDR; /* Interrupt Mask Register */ -#define AT91_SAMA5D2_IMR 0x2c + u16 IMR; /* Interrupt Status Register */ -#define AT91_SAMA5D2_ISR 0x30 + u16 ISR; +/* End of Conversion Interrupt Enable Register */ + u16 EOC_IER; +/* End of Conversion Interrupt Disable Register */ + u16 EOC_IDR; +/* End of Conversion Interrupt Mask Register */ + u16 EOC_IMR; +/* End of Conversion Interrupt Status Register */ + u16 EOC_ISR; /* Interrupt Status Register - Pen touching sense status */ #define AT91_SAMA5D2_ISR_PENS BIT(31) /* Last Channel Trigger Mode Register */ -#define AT91_SAMA5D2_LCTMR 0x34 + u16 LCTMR; /* Last Channel Compare Window Register */ -#define AT91_SAMA5D2_LCCWR 0x38 + u16 LCCWR; /* Overrun Status Register */ -#define AT91_SAMA5D2_OVER 0x3c + u16 OVER; /* Extended Mode Register */ -#define AT91_SAMA5D2_EMR 0x40 + u16 EMR; /* Extended Mode Register - Oversampling rate */ #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) @@ -134,24 +146,22 @@ /* Extended Mode Register - Averaging on single trigger event */ #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) + /* Compare Window Register */ -#define AT91_SAMA5D2_CWR 0x44 + u16 CWR; /* Channel Gain Register */ -#define AT91_SAMA5D2_CGR 0x48 - + u16 CGR; /* Channel Offset Register */ -#define AT91_SAMA5D2_COR 0x4c -#define AT91_SAMA5D2_COR_DIFF_OFFSET 16 - -/* Channel Data Register 0 */ -#define AT91_SAMA5D2_CDR0 0x50 + u16 COR; +/* Channel Offset Register differential offset - constant, not a register */ + u16 COR_diff_offset; /* Analog Control Register */ -#define AT91_SAMA5D2_ACR 0x94 + u16 ACR; /* Analog Control Register - Pen detect sensitivity mask */ #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) /* Touchscreen Mode Register */ -#define AT91_SAMA5D2_TSMR 0xb0 + u16 TSMR; /* Touchscreen Mode Register - No touch mode */ #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */ @@ -180,13 +190,13 @@ #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) /* Touchscreen X Position Register */ -#define AT91_SAMA5D2_XPOSR 0xb4 + u16 XPOSR; /* Touchscreen Y Position Register */ -#define AT91_SAMA5D2_YPOSR 0xb8 + u16 YPOSR; /* Touchscreen Pressure Register */ -#define AT91_SAMA5D2_PRESSR 0xbc + u16 PRESSR; /* Trigger Register */ -#define AT91_SAMA5D2_TRGR 0xc0 + u16 TRGR; /* Mask for TRGMOD field of TRGR register */ #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0) /* No trigger, only software trigger can start conversions */ @@ -205,30 +215,85 @@ #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16) /* Correction Select Register */ -#define AT91_SAMA5D2_COSR 0xd0 + u16 COSR; /* Correction Value Register */ -#define AT91_SAMA5D2_CVR 0xd4 + u16 CVR; /* Channel Error Correction Register */ -#define AT91_SAMA5D2_CECR 0xd8 + u16 CECR; /* Write Protection Mode Register */ -#define AT91_SAMA5D2_WPMR 0xe4 + u16 WPMR; /* Write Protection Status Register */ -#define AT91_SAMA5D2_WPSR 0xe8 + u16 WPSR; /* Version Register */ -#define AT91_SAMA5D2_VERSION 0xfc - -#define AT91_SAMA5D2_HW_TRIG_CNT 3 -#define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 -#define AT91_SAMA5D2_DIFF_CHAN_CNT 6 + u16 VERSION; +}; -#define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ - AT91_SAMA5D2_DIFF_CHAN_CNT + 1) +static const struct at91_adc_reg_layout sama5d2_layout = { + .CR = 0x00, + .MR = 0x04, + .SEQR1 = 0x08, + .SEQR2 = 0x0c, + .CHER = 0x10, + .CHDR = 0x14, + .CHSR = 0x18, + .LCDR = 0x20, + .IER = 0x24, + .IDR = 0x28, + .IMR = 0x2c, + .ISR = 0x30, + .LCTMR = 0x34, + .LCCWR = 0x38, + .OVER = 0x3c, + .EMR = 0x40, + .CWR = 0x44, + .CGR = 0x48, + .COR = 0x4c, + .COR_diff_offset = 16, + .ACR = 0x94, + .TSMR = 0xb0, + .XPOSR = 0xb4, + .YPOSR = 0xb8, + .PRESSR = 0xbc, + .TRGR = 0xc0, + .COSR = 0xd0, + .CVR = 0xd4, + .CECR = 0xd8, + .WPMR = 0xe4, + .WPSR = 0xe8, + .VERSION = 0xfc, +}; -#define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ - AT91_SAMA5D2_DIFF_CHAN_CNT * 2) -#define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) -#define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) -#define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX +static const struct at91_adc_reg_layout sama7g5_layout = { + .CR = 0x00, + .MR = 0x04, + .SEQR1 = 0x08, + .SEQR2 = 0x0c, + .CHER = 0x10, + .CHDR = 0x14, + .CHSR = 0x18, + .LCDR = 0x20, + .IER = 0x24, + .IDR = 0x28, + .IMR = 0x2c, + .ISR = 0x30, + .EOC_IER = 0x34, + .EOC_IDR = 0x38, + .EOC_IMR = 0x3c, + .EOC_ISR = 0x40, + .OVER = 0x4c, + .EMR = 0x50, + .CWR = 0x54, + .COR = 0x5c, + .COR_diff_offset = 0, + .ACR = 0xe0, + .TRGR = 0x100, + .COSR = 0x104, + .CVR = 0x108, + .CECR = 0x10c, + .WPMR = 0x118, + .WPSR = 0x11c, + .VERSION = 0x130, +}; #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 @@ -237,18 +302,6 @@ #define AT91_SAMA5D2_MAX_POS_BITS 12 -/* - * Maximum number of bytes to hold conversion from all channels - * without the timestamp. - */ -#define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \ - AT91_SAMA5D2_DIFF_CHAN_CNT) * 2) - -/* This total must also include the timestamp */ -#define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8) - -#define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2) - #define AT91_HWFIFO_MAX_SIZE_STR "128" #define AT91_HWFIFO_MAX_SIZE 128 @@ -257,12 +310,12 @@ #define AT91_OSR_4SAMPLES 4 #define AT91_OSR_16SAMPLES 16 -#define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \ +#define AT91_SAMA5D2_CHAN_SINGLE(index, num, addr) \ { \ .type = IIO_VOLTAGE, \ .channel = num, \ .address = addr, \ - .scan_index = num, \ + .scan_index = index, \ .scan_type = { \ .sign = 'u', \ .realbits = 14, \ @@ -276,14 +329,14 @@ .indexed = 1, \ } -#define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \ +#define AT91_SAMA5D2_CHAN_DIFF(index, num, num2, addr) \ { \ .type = IIO_VOLTAGE, \ .differential = 1, \ .channel = num, \ .channel2 = num2, \ .address = addr, \ - .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \ + .scan_index = index, \ .scan_type = { \ .sign = 's', \ .realbits = 14, \ @@ -330,13 +383,51 @@ .datasheet_name = name, \ } -#define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) -#define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) +#define at91_adc_readl(st, reg) \ + readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg) +#define at91_adc_read_chan(st, reg) \ + readl_relaxed((st)->base + reg) +#define at91_adc_writel(st, reg, val) \ + writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg) + +/** + * struct at91_adc_platform - at91-sama5d2 platform information struct + * @layout: pointer to the reg layout struct + * @adc_channels: pointer to an array of channels for registering in + * the iio subsystem + * @nr_channels: number of physical channels available + * @touch_chan_x: index of the touchscreen X channel + * @touch_chan_y: index of the touchscreen Y channel + * @touch_chan_p: index of the touchscreen P channel + * @max_channels: number of total channels + * @max_index: highest channel index (highest index may be higher + * than the total channel number) + * @hw_trig_cnt: number of possible hardware triggers + */ +struct at91_adc_platform { + const struct at91_adc_reg_layout *layout; + const struct iio_chan_spec (*adc_channels)[]; + unsigned int nr_channels; + unsigned int touch_chan_x; + unsigned int touch_chan_y; + unsigned int touch_chan_p; + unsigned int max_channels; + unsigned int max_index; + unsigned int hw_trig_cnt; +}; +/** + * struct at91_adc_soc_info - at91-sama5d2 soc information struct + * @startup_time: device startup time + * @min_sample_rate: minimum sample rate in Hz + * @max_sample_rate: maximum sample rate in Hz + * @platform: pointer to the platform structure + */ struct at91_adc_soc_info { unsigned startup_time; unsigned min_sample_rate; unsigned max_sample_rate; + const struct at91_adc_platform *platform; }; struct at91_adc_trigger { @@ -384,6 +475,15 @@ struct at91_adc_touch { struct work_struct workq; }; +/* + * Buffer size requirements: + * No channels * bytes_per_channel(2) + timestamp bytes (8) + * Divided by 2 because we need half words. + * We assume 32 channels for now, has to be increased if needed. + * Nobody minds a buffer being too big. + */ +#define AT91_BUFFER_MAX_HWORDS ((32 * 2 + 8) / 2) + struct at91_adc_state { void __iomem *base; int irq; @@ -439,29 +539,94 @@ static const struct at91_adc_trigger at91_adc_trigger_list[] = { }, }; -static const struct iio_chan_spec at91_adc_channels[] = { - AT91_SAMA5D2_CHAN_SINGLE(0, 0x50), - AT91_SAMA5D2_CHAN_SINGLE(1, 0x54), - AT91_SAMA5D2_CHAN_SINGLE(2, 0x58), - AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c), - AT91_SAMA5D2_CHAN_SINGLE(4, 0x60), - AT91_SAMA5D2_CHAN_SINGLE(5, 0x64), - AT91_SAMA5D2_CHAN_SINGLE(6, 0x68), - AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c), - AT91_SAMA5D2_CHAN_SINGLE(8, 0x70), - AT91_SAMA5D2_CHAN_SINGLE(9, 0x74), - AT91_SAMA5D2_CHAN_SINGLE(10, 0x78), - AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c), - AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50), - AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58), - AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60), - AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68), - AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70), - AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78), - IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX), - AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X), - AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y), - AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"), +static const struct iio_chan_spec at91_sama5d2_adc_channels[] = { + AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x50), + AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x54), + AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x58), + AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x5c), + AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x60), + AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x64), + AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x68), + AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x6c), + AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x70), + AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x74), + AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x78), + AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x7c), + /* original ABI has the differential channels with a gap in between */ + AT91_SAMA5D2_CHAN_DIFF(12, 0, 1, 0x50), + AT91_SAMA5D2_CHAN_DIFF(14, 2, 3, 0x58), + AT91_SAMA5D2_CHAN_DIFF(16, 4, 5, 0x60), + AT91_SAMA5D2_CHAN_DIFF(18, 6, 7, 0x68), + AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x70), + AT91_SAMA5D2_CHAN_DIFF(22, 10, 11, 0x78), + IIO_CHAN_SOFT_TIMESTAMP(23), + AT91_SAMA5D2_CHAN_TOUCH(24, "x", IIO_MOD_X), + AT91_SAMA5D2_CHAN_TOUCH(25, "y", IIO_MOD_Y), + AT91_SAMA5D2_CHAN_PRESSURE(26, "pressure"), +}; + +static const struct iio_chan_spec at91_sama7g5_adc_channels[] = { + AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x60), + AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x64), + AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x68), + AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x6c), + AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x70), + AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x74), + AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x78), + AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x7c), + AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x80), + AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x84), + AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x88), + AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x8c), + AT91_SAMA5D2_CHAN_SINGLE(12, 12, 0x90), + AT91_SAMA5D2_CHAN_SINGLE(13, 13, 0x94), + AT91_SAMA5D2_CHAN_SINGLE(14, 14, 0x98), + AT91_SAMA5D2_CHAN_SINGLE(15, 15, 0x9c), + AT91_SAMA5D2_CHAN_DIFF(16, 0, 1, 0x60), + AT91_SAMA5D2_CHAN_DIFF(17, 2, 3, 0x68), + AT91_SAMA5D2_CHAN_DIFF(18, 4, 5, 0x70), + AT91_SAMA5D2_CHAN_DIFF(19, 6, 7, 0x78), + AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x80), + AT91_SAMA5D2_CHAN_DIFF(21, 10, 11, 0x88), + AT91_SAMA5D2_CHAN_DIFF(22, 12, 13, 0x90), + AT91_SAMA5D2_CHAN_DIFF(23, 14, 15, 0x98), + IIO_CHAN_SOFT_TIMESTAMP(24), +}; + +static const struct at91_adc_platform sama5d2_platform = { + .layout = &sama5d2_layout, + .adc_channels = &at91_sama5d2_adc_channels, +#define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 +#define AT91_SAMA5D2_DIFF_CHAN_CNT 6 + .nr_channels = AT91_SAMA5D2_SINGLE_CHAN_CNT + + AT91_SAMA5D2_DIFF_CHAN_CNT, +#define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ + AT91_SAMA5D2_DIFF_CHAN_CNT * 2) + .touch_chan_x = AT91_SAMA5D2_TOUCH_X_CHAN_IDX, +#define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) + .touch_chan_y = AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, +#define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) + .touch_chan_p = AT91_SAMA5D2_TOUCH_P_CHAN_IDX, +#define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX + .max_channels = ARRAY_SIZE(at91_sama5d2_adc_channels), + .max_index = AT91_SAMA5D2_MAX_CHAN_IDX, +#define AT91_SAMA5D2_HW_TRIG_CNT 3 + .hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT, +}; + +static const struct at91_adc_platform sama7g5_platform = { + .layout = &sama7g5_layout, + .adc_channels = &at91_sama7g5_adc_channels, +#define AT91_SAMA7G5_SINGLE_CHAN_CNT 16 +#define AT91_SAMA7G5_DIFF_CHAN_CNT 8 + .nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT + + AT91_SAMA7G5_DIFF_CHAN_CNT, +#define AT91_SAMA7G5_MAX_CHAN_IDX (AT91_SAMA7G5_SINGLE_CHAN_CNT + \ + AT91_SAMA7G5_DIFF_CHAN_CNT) + .max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels), + .max_index = AT91_SAMA7G5_MAX_CHAN_IDX, +#define AT91_SAMA7G5_HW_TRIG_CNT 3 + .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT, }; static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -495,6 +660,7 @@ static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) { u32 mask = 0; u8 bit; + struct at91_adc_state *st = iio_priv(indio_dev); for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->num_channels) { @@ -503,13 +669,66 @@ static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) mask |= BIT(chan->channel); } - return mask & GENMASK(11, 0); + return mask & GENMASK(st->soc_info.platform->nr_channels, 0); +} + +static void at91_adc_cor(struct at91_adc_state *st, + struct iio_chan_spec const *chan) +{ + u32 cor, cur_cor; + + cor = BIT(chan->channel) | BIT(chan->channel2); + + cur_cor = at91_adc_readl(st, COR); + cor <<= st->soc_info.platform->layout->COR_diff_offset; + if (chan->differential) + at91_adc_writel(st, COR, cur_cor | cor); + else + at91_adc_writel(st, COR, cur_cor & ~cor); +} + +static void at91_adc_irq_status(struct at91_adc_state *st, u32 *status, + u32 *eoc) +{ + *status = at91_adc_readl(st, ISR); + if (st->soc_info.platform->layout->EOC_ISR) + *eoc = at91_adc_readl(st, EOC_ISR); + else + *eoc = *status; +} + +static void at91_adc_irq_mask(struct at91_adc_state *st, u32 *status, u32 *eoc) +{ + *status = at91_adc_readl(st, IMR); + if (st->soc_info.platform->layout->EOC_IMR) + *eoc = at91_adc_readl(st, EOC_IMR); + else + *eoc = *status; +} + +static void at91_adc_eoc_dis(struct at91_adc_state *st, unsigned int channel) +{ + /* + * On some products having the EOC bits in a separate register, + * errata recommends not writing this register (EOC_IDR). + * On products having the EOC bits in the IDR register, it's fine to write it. + */ + if (!st->soc_info.platform->layout->EOC_IDR) + at91_adc_writel(st, IDR, BIT(channel)); +} + +static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) +{ + if (!st->soc_info.platform->layout->EOC_IDR) + at91_adc_writel(st, IER, BIT(channel)); + else + at91_adc_writel(st, EOC_IER, BIT(channel)); } static void at91_adc_config_emr(struct at91_adc_state *st) { /* configure the extended mode register */ - unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR); + unsigned int emr = at91_adc_readl(st, EMR); /* select oversampling per single trigger event */ emr |= AT91_SAMA5D2_EMR_ASTE(1); @@ -533,7 +752,7 @@ static void at91_adc_config_emr(struct at91_adc_state *st) break; } - at91_adc_writel(st, AT91_SAMA5D2_EMR, emr); + at91_adc_writel(st, EMR, emr); } static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) @@ -586,9 +805,9 @@ static int at91_adc_configure_touch(struct at91_adc_state *st, bool state) if (!state) { /* disabling touch IRQs and setting mode to no touch enabled */ - at91_adc_writel(st, AT91_SAMA5D2_IDR, + at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN); - at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0); + at91_adc_writel(st, TSMR, 0); return 0; } /* @@ -614,26 +833,26 @@ static int at91_adc_configure_touch(struct at91_adc_state *st, bool state) tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA; tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK; - at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr); + at91_adc_writel(st, TSMR, tsmr); - acr = at91_adc_readl(st, AT91_SAMA5D2_ACR); + acr = at91_adc_readl(st, ACR); acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK; acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK; - at91_adc_writel(st, AT91_SAMA5D2_ACR, acr); + at91_adc_writel(st, ACR, acr); /* Sample Period Time = (TRGPER + 1) / ADCClock */ st->touch_st.sample_period_val = round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US * clk_khz / 1000) - 1, 1); /* enable pen detect IRQ */ - at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); + at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN); return 0; } static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) { - u32 val; + u32 val = 0; u32 scale, result, pos; /* @@ -642,7 +861,11 @@ static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1 */ /* first half of register is the x or y, second half is the scale */ - val = at91_adc_readl(st, reg); + if (reg == st->soc_info.platform->layout->XPOSR) + val = at91_adc_readl(st, XPOSR); + else if (reg == st->soc_info.platform->layout->YPOSR) + val = at91_adc_readl(st, YPOSR); + if (!val) dev_dbg(&st->indio_dev->dev, "pos is 0\n"); @@ -660,13 +883,13 @@ static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) static u16 at91_adc_touch_x_pos(struct at91_adc_state *st) { - st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR); + st->touch_st.x_pos = at91_adc_touch_pos(st, st->soc_info.platform->layout->XPOSR); return st->touch_st.x_pos; } static u16 at91_adc_touch_y_pos(struct at91_adc_state *st) { - return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR); + return at91_adc_touch_pos(st, st->soc_info.platform->layout->YPOSR); } static u16 at91_adc_touch_pressure(struct at91_adc_state *st) @@ -678,7 +901,7 @@ static u16 at91_adc_touch_pressure(struct at91_adc_state *st) u32 factor = 1000; /* calculate the pressure */ - val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); + val = at91_adc_readl(st, PRESSR); z1 = val & AT91_SAMA5D2_XYZ_MASK; z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; @@ -702,9 +925,9 @@ static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val) *val = 0; if (!st->touch_st.touching) return -ENODATA; - if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX) + if (chan == st->soc_info.platform->touch_chan_x) *val = at91_adc_touch_x_pos(st); - else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX) + else if (chan == st->soc_info.platform->touch_chan_y) *val = at91_adc_touch_y_pos(st); else return -ENODATA; @@ -717,7 +940,7 @@ static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val) *val = 0; if (!st->touch_st.touching) return -ENODATA; - if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX) + if (chan == st->soc_info.platform->touch_chan_p) *val = at91_adc_touch_pressure(st); else return -ENODATA; @@ -729,7 +952,7 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) { struct iio_dev *indio = iio_trigger_get_drvdata(trig); struct at91_adc_state *st = iio_priv(indio); - u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR); + u32 status = at91_adc_readl(st, TRGR); /* clear TRGMOD */ status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK; @@ -738,7 +961,7 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) status |= st->selected_trig->trgmod_value; /* set/unset hw trigger */ - at91_adc_writel(st, AT91_SAMA5D2_TRGR, status); + at91_adc_writel(st, TRGR, status); return 0; } @@ -755,7 +978,7 @@ static void at91_adc_reenable_trigger(struct iio_trigger *trig) enable_irq(st->irq); /* Needed to ACK the DRDY interruption */ - at91_adc_readl(st, AT91_SAMA5D2_LCDR); + at91_adc_readl(st, LCDR); } static const struct iio_trigger_ops at91_adc_trigger_ops = { @@ -850,7 +1073,7 @@ static int at91_adc_dma_start(struct iio_dev *indio_dev) } /* enable general overrun error signaling */ - at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE); + at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE); /* Issue pending DMA requests */ dma_async_issue_pending(st->dma_st.dma_chan); @@ -880,7 +1103,7 @@ static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev) return !!bitmap_subset(indio_dev->active_scan_mask, &st->touch_st.channels_bitmask, - AT91_SAMA5D2_MAX_CHAN_IDX + 1); + st->soc_info.platform->max_index + 1); } static int at91_adc_buffer_prepare(struct iio_dev *indio_dev) @@ -908,8 +1131,6 @@ static int at91_adc_buffer_prepare(struct iio_dev *indio_dev) indio_dev->num_channels) { struct iio_chan_spec const *chan = at91_adc_chan_get(indio_dev, bit); - u32 cor; - if (!chan) continue; /* these channel types cannot be handled by this trigger */ @@ -917,22 +1138,13 @@ static int at91_adc_buffer_prepare(struct iio_dev *indio_dev) chan->type == IIO_PRESSURE) continue; - cor = at91_adc_readl(st, AT91_SAMA5D2_COR); - - if (chan->differential) - cor |= (BIT(chan->channel) | BIT(chan->channel2)) << - AT91_SAMA5D2_COR_DIFF_OFFSET; - else - cor &= ~(BIT(chan->channel) << - AT91_SAMA5D2_COR_DIFF_OFFSET); - - at91_adc_writel(st, AT91_SAMA5D2_COR, cor); + at91_adc_cor(st, chan); - at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); + at91_adc_writel(st, CHER, BIT(chan->channel)); } if (at91_adc_buffer_check_use_irq(indio_dev, st)) - at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY); + at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY); return 0; } @@ -968,17 +1180,17 @@ static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) chan->type == IIO_PRESSURE) continue; - at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); + at91_adc_writel(st, CHDR, BIT(chan->channel)); if (st->dma_st.dma_chan) - at91_adc_readl(st, chan->address); + at91_adc_read_chan(st, chan->address); } if (at91_adc_buffer_check_use_irq(indio_dev, st)) - at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY); + at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY); /* read overflow register to clear possible overflow status */ - at91_adc_readl(st, AT91_SAMA5D2_OVER); + at91_adc_readl(st, OVER); /* if we are using DMA we must clear registers and end DMA */ if (st->dma_st.dma_chan) @@ -1021,13 +1233,15 @@ static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, u8 bit; u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); unsigned int timeout = 50; + u32 status, imr, eoc = 0, eoc_imr; /* * Check if the conversion is ready. If not, wait a little bit, and * in case of timeout exit with an error. */ - while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask && - timeout) { + while (((eoc & mask) != mask) && timeout) { + at91_adc_irq_status(st, &status, &eoc); + at91_adc_irq_mask(st, &imr, &eoc_imr); usleep_range(50, 100); timeout--; } @@ -1054,7 +1268,7 @@ static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, * Thus, emit a warning. */ if (chan->type == IIO_VOLTAGE) { - val = at91_adc_readl(st, chan->address); + val = at91_adc_read_chan(st, chan->address); at91_adc_adjust_val_osr(st, &val); st->buffer[i] = val; } else { @@ -1075,7 +1289,7 @@ static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev) s64 interval; int sample_index = 0, sample_count, sample_size; - u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); + u32 status = at91_adc_readl(st, ISR); /* if we reached this point, we cannot sample faster */ if (status & AT91_SAMA5D2_IER_GOVRE) pr_info_ratelimited("%s: conversion overrun detected\n", @@ -1127,7 +1341,7 @@ static irqreturn_t at91_adc_trigger_handler(int irq, void *p) * actually polling the trigger now. */ if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev)) - at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); + at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START); if (st->dma_st.dma_chan) at91_adc_trigger_handler_dma(indio_dev); @@ -1174,11 +1388,11 @@ static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq) startup = at91_adc_startup_time(st->soc_info.startup_time, freq / 1000); - mr = at91_adc_readl(st, AT91_SAMA5D2_MR); + mr = at91_adc_readl(st, MR); mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK); mr |= AT91_SAMA5D2_MR_STARTUP(startup); mr |= AT91_SAMA5D2_MR_PRESCAL(prescal); - at91_adc_writel(st, AT91_SAMA5D2_MR, mr); + at91_adc_writel(st, MR, mr); dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n", freq, startup, prescal); @@ -1198,7 +1412,7 @@ static void at91_adc_touch_data_handler(struct iio_dev *indio_dev) int i = 0; for_each_set_bit(bit, indio_dev->active_scan_mask, - AT91_SAMA5D2_MAX_CHAN_IDX + 1) { + st->soc_info.platform->max_index + 1) { struct iio_chan_spec const *chan = at91_adc_chan_get(indio_dev, bit); @@ -1224,12 +1438,11 @@ static void at91_adc_touch_data_handler(struct iio_dev *indio_dev) static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st) { - at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN); - at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN | + at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN); + at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN | AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | AT91_SAMA5D2_IER_PRDY); - at91_adc_writel(st, AT91_SAMA5D2_TRGR, - AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC | + at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC | AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val)); st->touch_st.touching = true; } @@ -1238,16 +1451,15 @@ static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev) { struct at91_adc_state *st = iio_priv(indio_dev); - at91_adc_writel(st, AT91_SAMA5D2_TRGR, - AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER); - at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN | + at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER); + at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN | AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | AT91_SAMA5D2_IER_PRDY); st->touch_st.touching = false; at91_adc_touch_data_handler(indio_dev); - at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); + at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN); } static void at91_adc_workq_handler(struct work_struct *workq) @@ -1265,12 +1477,14 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private) { struct iio_dev *indio = private; struct at91_adc_state *st = iio_priv(indio); - u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); - u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR); + u32 status, eoc, imr, eoc_imr; u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | AT91_SAMA5D2_IER_PRDY; - if (!(status & imr)) + at91_adc_irq_status(st, &status, &eoc); + at91_adc_irq_mask(st, &imr, &eoc_imr); + + if (!(status & imr) && !(eoc & eoc_imr)) return IRQ_NONE; if (status & AT91_SAMA5D2_IER_PEN) { /* pen detected IRQ */ @@ -1287,9 +1501,9 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private) * touching, but the measurements are not ready yet. * read and ignore. */ - status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR); - status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR); - status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); + status = at91_adc_readl(st, XPOSR); + status = at91_adc_readl(st, YPOSR); + status = at91_adc_readl(st, PRESSR); } else if (iio_buffer_enabled(indio) && (status & AT91_SAMA5D2_IER_DRDY)) { /* triggered buffer without DMA */ @@ -1301,7 +1515,7 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private) WARN(true, "Unexpected irq occurred\n"); } else if (!iio_buffer_enabled(indio)) { /* software requested conversion */ - st->conversion_value = at91_adc_readl(st, st->chan->address); + st->conversion_value = at91_adc_read_chan(st, st->chan->address); st->conversion_done = true; wake_up_interruptible(&st->wq_data_available); } @@ -1312,7 +1526,6 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { struct at91_adc_state *st = iio_priv(indio_dev); - u32 cor = 0; u16 tmp_val; int ret; @@ -1358,14 +1571,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, st->chan = chan; - if (chan->differential) - cor = (BIT(chan->channel) | BIT(chan->channel2)) << - AT91_SAMA5D2_COR_DIFF_OFFSET; - - at91_adc_writel(st, AT91_SAMA5D2_COR, cor); - at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); - at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel)); - at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); + at91_adc_cor(st, chan); + at91_adc_writel(st, CHER, BIT(chan->channel)); + at91_adc_eoc_ena(st, chan->channel); + at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START); ret = wait_event_interruptible_timeout(st->wq_data_available, st->conversion_done, @@ -1381,11 +1590,11 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, st->conversion_done = false; } - at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel)); - at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); + at91_adc_eoc_dis(st, st->chan->channel); + at91_adc_writel(st, CHDR, BIT(chan->channel)); /* Needed to ACK the DRDY interruption */ - at91_adc_readl(st, AT91_SAMA5D2_LCDR); + at91_adc_readl(st, LCDR); mutex_unlock(&st->lock); @@ -1457,14 +1666,15 @@ static void at91_adc_dma_init(struct platform_device *pdev) struct iio_dev *indio_dev = platform_get_drvdata(pdev); struct at91_adc_state *st = iio_priv(indio_dev); struct dma_slave_config config = {0}; + /* we have 2 bytes for each channel */ + unsigned int sample_size = st->soc_info.platform->nr_channels * 2; /* * We make the buffer double the size of the fifo, * such that DMA uses one half of the buffer (full fifo size) * and the software uses the other half to read/write. */ unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * - AT91_BUFFER_MAX_CONVERSION_BYTES * 2, - PAGE_SIZE); + sample_size * 2, PAGE_SIZE); if (st->dma_st.dma_chan) return; @@ -1488,7 +1698,7 @@ static void at91_adc_dma_init(struct platform_device *pdev) /* Configure DMA channel to read data register */ config.direction = DMA_DEV_TO_MEM; config.src_addr = (phys_addr_t)(st->dma_st.phys_addr - + AT91_SAMA5D2_LCDR); + + st->soc_info.platform->layout->LCDR); config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; config.src_maxburst = 1; config.dst_maxburst = 1; @@ -1517,9 +1727,10 @@ static void at91_adc_dma_disable(struct platform_device *pdev) { struct iio_dev *indio_dev = platform_get_drvdata(pdev); struct at91_adc_state *st = iio_priv(indio_dev); + /* we have 2 bytes for each channel */ + unsigned int sample_size = st->soc_info.platform->nr_channels * 2; unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * - AT91_BUFFER_MAX_CONVERSION_BYTES * 2, - PAGE_SIZE); + sample_size * 2, PAGE_SIZE); /* if we are not using DMA, just return */ if (!st->dma_st.dma_chan) @@ -1580,14 +1791,14 @@ static int at91_adc_update_scan_mode(struct iio_dev *indio_dev, struct at91_adc_state *st = iio_priv(indio_dev); if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask, - AT91_SAMA5D2_MAX_CHAN_IDX + 1)) + st->soc_info.platform->max_index + 1)) return 0; /* * if the new bitmap is a combination of touchscreen and regular * channels, then we are not fine */ if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask, - AT91_SAMA5D2_MAX_CHAN_IDX + 1)) + st->soc_info.platform->max_index + 1)) return -EINVAL; return 0; } @@ -1596,13 +1807,15 @@ static void at91_adc_hw_init(struct iio_dev *indio_dev) { struct at91_adc_state *st = iio_priv(indio_dev); - at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); - at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff); + at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST); + if (st->soc_info.platform->layout->EOC_IDR) + at91_adc_writel(st, EOC_IDR, 0xffffffff); + at91_adc_writel(st, IDR, 0xffffffff); /* * Transfer field must be set to 2 according to the datasheet and * allows different analog settings for each channel. */ - at91_adc_writel(st, AT91_SAMA5D2_MR, + at91_adc_writel(st, MR, AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH); at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate); @@ -1681,8 +1894,8 @@ static int at91_adc_buffer_and_trigger_init(struct device *dev, fifo_attrs = NULL; ret = devm_iio_triggered_buffer_setup_ext(&indio->dev, indio, - &iio_pollfunc_store_time, - &at91_adc_trigger_handler, &at91_buffer_setup_ops, fifo_attrs); + &iio_pollfunc_store_time, &at91_adc_trigger_handler, + IIO_BUFFER_DIRECTION_IN, &at91_buffer_setup_ops, fifo_attrs); if (ret < 0) { dev_err(dev, "couldn't initialize the buffer.\n"); return ret; @@ -1718,21 +1931,23 @@ static int at91_adc_probe(struct platform_device *pdev) if (!indio_dev) return -ENOMEM; + st = iio_priv(indio_dev); + st->indio_dev = indio_dev; + + st->soc_info.platform = of_device_get_match_data(&pdev->dev); + indio_dev->name = dev_name(&pdev->dev); indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; indio_dev->info = &at91_adc_info; - indio_dev->channels = at91_adc_channels; - indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels); - - st = iio_priv(indio_dev); - st->indio_dev = indio_dev; + indio_dev->channels = *st->soc_info.platform->adc_channels; + indio_dev->num_channels = st->soc_info.platform->max_channels; bitmap_set(&st->touch_st.channels_bitmask, - AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1); + st->soc_info.platform->touch_chan_x, 1); bitmap_set(&st->touch_st.channels_bitmask, - AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1); + st->soc_info.platform->touch_chan_y, 1); bitmap_set(&st->touch_st.channels_bitmask, - AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1); + st->soc_info.platform->touch_chan_p, 1); st->oversampling_ratio = AT91_OSR_1SAMPLES; @@ -1772,7 +1987,7 @@ static int at91_adc_probe(struct platform_device *pdev) st->selected_trig = NULL; /* find the right trigger, or no trigger at all */ - for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++) + for (i = 0; i < st->soc_info.platform->hw_trig_cnt + 1; i++) if (at91_adc_trigger_list[i].edge_type == edge_type) { st->selected_trig = &at91_adc_trigger_list[i]; break; @@ -1833,12 +2048,12 @@ static int at91_adc_probe(struct platform_device *pdev) goto vref_disable; } - at91_adc_hw_init(indio_dev); - ret = clk_prepare_enable(st->per_clk); if (ret) goto vref_disable; + at91_adc_hw_init(indio_dev); + platform_set_drvdata(pdev, indio_dev); ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev); @@ -1857,7 +2072,7 @@ static int at91_adc_probe(struct platform_device *pdev) st->selected_trig->name); dev_info(&pdev->dev, "version: %x\n", - readl_relaxed(st->base + AT91_SAMA5D2_VERSION)); + readl_relaxed(st->base + st->soc_info.platform->layout->VERSION)); return 0; @@ -1900,7 +2115,7 @@ static __maybe_unused int at91_adc_suspend(struct device *dev) * and can be used by for other devices. * Otherwise, ADC will hog them and we can't go to suspend mode. */ - at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); + at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST); clk_disable_unprepare(st->per_clk); regulator_disable(st->vref); @@ -1960,6 +2175,10 @@ static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); static const struct of_device_id at91_adc_dt_match[] = { { .compatible = "atmel,sama5d2-adc", + .data = (const void *)&sama5d2_platform, + }, { + .compatible = "microchip,sama7g5-adc", + .data = (const void *)&sama7g5_platform, }, { /* sentinel */ } @@ -1977,6 +2196,7 @@ static struct platform_driver at91_adc_driver = { }; module_platform_driver(at91_adc_driver) -MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); +MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@microchip.com>"); +MODULE_AUTHOR("Eugen Hristev <eugen.hristev@microchip.com"); MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/adc/axp288_adc.c b/drivers/iio/adc/axp288_adc.c index 5f5e8b39e4d2..a4b8be5b8f88 100644 --- a/drivers/iio/adc/axp288_adc.c +++ b/drivers/iio/adc/axp288_adc.c @@ -259,7 +259,7 @@ static int axp288_adc_probe(struct platform_device *pdev) info->irq = platform_get_irq(pdev, 0); if (info->irq < 0) return info->irq; - platform_set_drvdata(pdev, indio_dev); + info->regmap = axp20x->regmap; /* * Set ADC to enabled state at all time, including system suspend. @@ -276,31 +276,12 @@ static int axp288_adc_probe(struct platform_device *pdev) indio_dev->num_channels = ARRAY_SIZE(axp288_adc_channels); indio_dev->info = &axp288_adc_iio_info; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_map_array_register(indio_dev, axp288_adc_default_maps); + + ret = devm_iio_map_array_register(&pdev->dev, indio_dev, axp288_adc_default_maps); if (ret < 0) return ret; - ret = iio_device_register(indio_dev); - if (ret < 0) { - dev_err(&pdev->dev, "unable to register iio device\n"); - goto err_array_unregister; - } - return 0; - -err_array_unregister: - iio_map_array_unregister(indio_dev); - - return ret; -} - -static int axp288_adc_remove(struct platform_device *pdev) -{ - struct iio_dev *indio_dev = platform_get_drvdata(pdev); - - iio_device_unregister(indio_dev); - iio_map_array_unregister(indio_dev); - - return 0; + return devm_iio_device_register(&pdev->dev, indio_dev); } static const struct platform_device_id axp288_adc_id_table[] = { @@ -310,7 +291,6 @@ static const struct platform_device_id axp288_adc_id_table[] = { static struct platform_driver axp288_adc_driver = { .probe = axp288_adc_probe, - .remove = axp288_adc_remove, .id_table = axp288_adc_id_table, .driver = { .name = "axp288_adc", diff --git a/drivers/iio/adc/berlin2-adc.c b/drivers/iio/adc/berlin2-adc.c index 8b04b95b7b7a..03987d7e6b3d 100644 --- a/drivers/iio/adc/berlin2-adc.c +++ b/drivers/iio/adc/berlin2-adc.c @@ -280,6 +280,13 @@ static const struct iio_info berlin2_adc_info = { .read_raw = berlin2_adc_read_raw, }; +static void berlin2_adc_powerdown(void *regmap) +{ + regmap_update_bits(regmap, BERLIN2_SM_CTRL, + BERLIN2_SM_CTRL_ADC_POWER, 0); + +} + static int berlin2_adc_probe(struct platform_device *pdev) { struct iio_dev *indio_dev; @@ -293,7 +300,6 @@ static int berlin2_adc_probe(struct platform_device *pdev) return -ENOMEM; priv = iio_priv(indio_dev); - platform_set_drvdata(pdev, indio_dev); priv->regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); @@ -333,29 +339,12 @@ static int berlin2_adc_probe(struct platform_device *pdev) BERLIN2_SM_CTRL_ADC_POWER, BERLIN2_SM_CTRL_ADC_POWER); - ret = iio_device_register(indio_dev); - if (ret) { - /* Power down the ADC */ - regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL, - BERLIN2_SM_CTRL_ADC_POWER, 0); + ret = devm_add_action_or_reset(&pdev->dev, berlin2_adc_powerdown, + priv->regmap); + if (ret) return ret; - } - - return 0; -} - -static int berlin2_adc_remove(struct platform_device *pdev) -{ - struct iio_dev *indio_dev = platform_get_drvdata(pdev); - struct berlin2_adc_priv *priv = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - - /* Power down the ADC */ - regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL, - BERLIN2_SM_CTRL_ADC_POWER, 0); - return 0; + return devm_iio_device_register(&pdev->dev, indio_dev); } static const struct of_device_id berlin2_adc_match[] = { @@ -370,7 +359,6 @@ static struct platform_driver berlin2_adc_driver = { .of_match_table = berlin2_adc_match, }, .probe = berlin2_adc_probe, - .remove = berlin2_adc_remove, }; module_platform_driver(berlin2_adc_driver); diff --git a/drivers/iio/adc/da9150-gpadc.c b/drivers/iio/adc/da9150-gpadc.c index 7a7a54a7ed76..8f0d3fb63b67 100644 --- a/drivers/iio/adc/da9150-gpadc.c +++ b/drivers/iio/adc/da9150-gpadc.c @@ -330,7 +330,6 @@ static int da9150_gpadc_probe(struct platform_device *pdev) } gpadc = iio_priv(indio_dev); - platform_set_drvdata(pdev, indio_dev); gpadc->da9150 = da9150; gpadc->dev = dev; mutex_init(&gpadc->lock); @@ -347,7 +346,7 @@ static int da9150_gpadc_probe(struct platform_device *pdev) return ret; } - ret = iio_map_array_register(indio_dev, da9150_gpadc_default_maps); + ret = devm_iio_map_array_register(&pdev->dev, indio_dev, da9150_gpadc_default_maps); if (ret) { dev_err(dev, "Failed to register IIO maps: %d\n", ret); return ret; @@ -359,28 +358,7 @@ static int da9150_gpadc_probe(struct platform_device *pdev) indio_dev->channels = da9150_gpadc_channels; indio_dev->num_channels = ARRAY_SIZE(da9150_gpadc_channels); - ret = iio_device_register(indio_dev); - if (ret) { - dev_err(dev, "Failed to register IIO device: %d\n", ret); - goto iio_map_unreg; - } - - return 0; - -iio_map_unreg: - iio_map_array_unregister(indio_dev); - - return ret; -} - -static int da9150_gpadc_remove(struct platform_device *pdev) -{ - struct iio_dev *indio_dev = platform_get_drvdata(pdev); - - iio_device_unregister(indio_dev); - iio_map_array_unregister(indio_dev); - - return 0; + return devm_iio_device_register(&pdev->dev, indio_dev); } static struct platform_driver da9150_gpadc_driver = { @@ -388,7 +366,6 @@ static struct platform_driver da9150_gpadc_driver = { .name = "da9150-gpadc", }, .probe = da9150_gpadc_probe, - .remove = da9150_gpadc_remove, }; module_platform_driver(da9150_gpadc_driver); diff --git a/drivers/iio/adc/ep93xx_adc.c b/drivers/iio/adc/ep93xx_adc.c index 8edd6407b7c3..fd5a9404c8dc 100644 --- a/drivers/iio/adc/ep93xx_adc.c +++ b/drivers/iio/adc/ep93xx_adc.c @@ -156,15 +156,13 @@ static int ep93xx_adc_probe(struct platform_device *pdev) struct iio_dev *iiodev; struct ep93xx_adc_priv *priv; struct clk *pclk; - struct resource *res; iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv)); if (!iiodev) return -ENOMEM; priv = iio_priv(iiodev); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->base = devm_ioremap_resource(&pdev->dev, res); + priv->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); diff --git a/drivers/iio/adc/fsl-imx25-gcq.c b/drivers/iio/adc/fsl-imx25-gcq.c index 329c555b55cc..551e83ae573c 100644 --- a/drivers/iio/adc/fsl-imx25-gcq.c +++ b/drivers/iio/adc/fsl-imx25-gcq.c @@ -172,13 +172,35 @@ static const struct regmap_config mx25_gcq_regconfig = { .reg_stride = 4, }; +static int mx25_gcq_ext_regulator_setup(struct device *dev, + struct mx25_gcq_priv *priv, u32 refp) +{ + char reg_name[12]; + int ret; + + if (priv->vref[refp]) + return 0; + + ret = snprintf(reg_name, sizeof(reg_name), "vref-%s", + mx25_gcq_refp_names[refp]); + if (ret < 0) + return ret; + + priv->vref[refp] = devm_regulator_get_optional(dev, reg_name); + if (IS_ERR(priv->vref[refp])) + return dev_err_probe(dev, PTR_ERR(priv->vref[refp]), + "Error, trying to use external voltage reference without a %s regulator.", + reg_name); + + return 0; +} + static int mx25_gcq_setup_cfgs(struct platform_device *pdev, struct mx25_gcq_priv *priv) { struct device_node *np = pdev->dev.of_node; struct device_node *child; struct device *dev = &pdev->dev; - unsigned int refp_used[4] = {}; int ret, i; /* @@ -194,19 +216,6 @@ static int mx25_gcq_setup_cfgs(struct platform_device *pdev, MX25_ADCQ_CFG_IN(i) | MX25_ADCQ_CFG_REFN_NGND2); - /* - * First get all regulators to store them in channel_vref_mv if - * necessary. Later we use that information for proper IIO scale - * information. - */ - priv->vref[MX25_ADC_REFP_INT] = NULL; - priv->vref[MX25_ADC_REFP_EXT] = - devm_regulator_get_optional(dev, "vref-ext"); - priv->vref[MX25_ADC_REFP_XP] = - devm_regulator_get_optional(dev, "vref-xp"); - priv->vref[MX25_ADC_REFP_YP] = - devm_regulator_get_optional(dev, "vref-yp"); - for_each_child_of_node(np, child) { u32 reg; u32 refp = MX25_ADCQ_CFG_REFP_INT; @@ -233,11 +242,10 @@ static int mx25_gcq_setup_cfgs(struct platform_device *pdev, case MX25_ADC_REFP_EXT: case MX25_ADC_REFP_XP: case MX25_ADC_REFP_YP: - if (IS_ERR(priv->vref[refp])) { - dev_err(dev, "Error, trying to use external voltage reference without a vref-%s regulator.", - mx25_gcq_refp_names[refp]); + ret = mx25_gcq_ext_regulator_setup(&pdev->dev, priv, refp); + if (ret) { of_node_put(child); - return PTR_ERR(priv->vref[refp]); + return ret; } priv->channel_vref_mv[reg] = regulator_get_voltage(priv->vref[refp]); @@ -253,8 +261,6 @@ static int mx25_gcq_setup_cfgs(struct platform_device *pdev, return -EINVAL; } - ++refp_used[refp]; - /* * Shift the read values to the correct positions within the * register. @@ -285,15 +291,6 @@ static int mx25_gcq_setup_cfgs(struct platform_device *pdev, regmap_write(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_PDMSK | MX25_ADCQ_CR_QSM_FQS); - /* Remove unused regulators */ - for (i = 0; i != 4; ++i) { - if (!refp_used[i]) { - if (!IS_ERR_OR_NULL(priv->vref[i])) - devm_regulator_put(priv->vref[i]); - priv->vref[i] = NULL; - } - } - return 0; } diff --git a/drivers/iio/adc/imx7d_adc.c b/drivers/iio/adc/imx7d_adc.c index 4969a5f941e3..092f8d296527 100644 --- a/drivers/iio/adc/imx7d_adc.c +++ b/drivers/iio/adc/imx7d_adc.c @@ -493,22 +493,16 @@ static int imx7d_adc_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) - return irq; + return dev_err_probe(dev, irq, "Failed getting irq\n"); info->clk = devm_clk_get(dev, "adc"); - if (IS_ERR(info->clk)) { - ret = PTR_ERR(info->clk); - dev_err(dev, "Failed getting clock, err = %d\n", ret); - return ret; - } + if (IS_ERR(info->clk)) + return dev_err_probe(dev, PTR_ERR(info->clk), "Failed getting clock\n"); info->vref = devm_regulator_get(dev, "vref"); - if (IS_ERR(info->vref)) { - ret = PTR_ERR(info->vref); - dev_err(dev, - "Failed getting reference voltage, err = %d\n", ret); - return ret; - } + if (IS_ERR(info->vref)) + return dev_err_probe(dev, PTR_ERR(info->vref), + "Failed getting reference voltage\n"); platform_set_drvdata(pdev, indio_dev); diff --git a/drivers/iio/adc/imx8qxp-adc.c b/drivers/iio/adc/imx8qxp-adc.c new file mode 100644 index 000000000000..901dd8e1b32f --- /dev/null +++ b/drivers/iio/adc/imx8qxp-adc.c @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NXP i.MX8QXP ADC driver + * + * Based on the work of Haibo Chen <haibo.chen@nxp.com> + * The initial developer of the original code is Haibo Chen. + * Portions created by Haibo Chen are Copyright (C) 2018 NXP. + * All Rights Reserved. + * + * Copyright (C) 2018 NXP + * Copyright (C) 2021 Cai Huoqing + */ +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regulator/consumer.h> + +#include <linux/iio/iio.h> + +#define ADC_DRIVER_NAME "imx8qxp-adc" + +/* Register map definition */ +#define IMX8QXP_ADR_ADC_CTRL 0x10 +#define IMX8QXP_ADR_ADC_STAT 0x14 +#define IMX8QXP_ADR_ADC_IE 0x18 +#define IMX8QXP_ADR_ADC_DE 0x1c +#define IMX8QXP_ADR_ADC_CFG 0x20 +#define IMX8QXP_ADR_ADC_FCTRL 0x30 +#define IMX8QXP_ADR_ADC_SWTRIG 0x34 +#define IMX8QXP_ADR_ADC_TCTRL(tid) (0xc0 + (tid) * 4) +#define IMX8QXP_ADR_ADC_CMDH(cid) (0x100 + (cid) * 8) +#define IMX8QXP_ADR_ADC_CMDL(cid) (0x104 + (cid) * 8) +#define IMX8QXP_ADR_ADC_RESFIFO 0x300 +#define IMX8QXP_ADR_ADC_TST 0xffc + +/* ADC bit shift */ +#define IMX8QXP_ADC_IE_FWMIE_MASK GENMASK(1, 0) +#define IMX8QXP_ADC_CTRL_FIFO_RESET_MASK BIT(8) +#define IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK BIT(1) +#define IMX8QXP_ADC_CTRL_ADC_EN_MASK BIT(0) +#define IMX8QXP_ADC_TCTRL_TCMD_MASK GENMASK(31, 24) +#define IMX8QXP_ADC_TCTRL_TDLY_MASK GENMASK(23, 16) +#define IMX8QXP_ADC_TCTRL_TPRI_MASK GENMASK(15, 8) +#define IMX8QXP_ADC_TCTRL_HTEN_MASK GENMASK(7, 0) +#define IMX8QXP_ADC_CMDL_CSCALE_MASK GENMASK(13, 8) +#define IMX8QXP_ADC_CMDL_MODE_MASK BIT(7) +#define IMX8QXP_ADC_CMDL_DIFF_MASK BIT(6) +#define IMX8QXP_ADC_CMDL_ABSEL_MASK BIT(5) +#define IMX8QXP_ADC_CMDL_ADCH_MASK GENMASK(2, 0) +#define IMX8QXP_ADC_CMDH_NEXT_MASK GENMASK(31, 24) +#define IMX8QXP_ADC_CMDH_LOOP_MASK GENMASK(23, 16) +#define IMX8QXP_ADC_CMDH_AVGS_MASK GENMASK(15, 12) +#define IMX8QXP_ADC_CMDH_STS_MASK BIT(8) +#define IMX8QXP_ADC_CMDH_LWI_MASK GENMASK(7, 7) +#define IMX8QXP_ADC_CMDH_CMPEN_MASK GENMASK(0, 0) +#define IMX8QXP_ADC_CFG_PWREN_MASK BIT(28) +#define IMX8QXP_ADC_CFG_PUDLY_MASK GENMASK(23, 16) +#define IMX8QXP_ADC_CFG_REFSEL_MASK GENMASK(7, 6) +#define IMX8QXP_ADC_CFG_PWRSEL_MASK GENMASK(5, 4) +#define IMX8QXP_ADC_CFG_TPRICTRL_MASK GENMASK(3, 0) +#define IMX8QXP_ADC_FCTRL_FWMARK_MASK GENMASK(20, 16) +#define IMX8QXP_ADC_FCTRL_FCOUNT_MASK GENMASK(4, 0) +#define IMX8QXP_ADC_RESFIFO_VAL_MASK GENMASK(18, 3) + +/* ADC PARAMETER*/ +#define IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL GENMASK(5, 0) +#define IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL 0 +#define IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION 0 +#define IMX8QXP_ADC_CMDL_MODE_SINGLE 0 +#define IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS 0 +#define IMX8QXP_ADC_CMDH_CMPEN_DIS 0 +#define IMX8QXP_ADC_PAUSE_EN BIT(31) +#define IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH 0 + +#define IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS 0 + +#define IMX8QXP_ADC_TIMEOUT msecs_to_jiffies(100) + +struct imx8qxp_adc { + struct device *dev; + void __iomem *regs; + struct clk *clk; + struct clk *ipg_clk; + struct regulator *vref; + /* Serialise ADC channel reads */ + struct mutex lock; + struct completion completion; +}; + +#define IMX8QXP_ADC_CHAN(_idx) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = (_idx), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ +} + +static const struct iio_chan_spec imx8qxp_adc_iio_channels[] = { + IMX8QXP_ADC_CHAN(0), + IMX8QXP_ADC_CHAN(1), + IMX8QXP_ADC_CHAN(2), + IMX8QXP_ADC_CHAN(3), + IMX8QXP_ADC_CHAN(4), + IMX8QXP_ADC_CHAN(5), + IMX8QXP_ADC_CHAN(6), + IMX8QXP_ADC_CHAN(7), +}; + +static void imx8qxp_adc_reset(struct imx8qxp_adc *adc) +{ + u32 ctrl; + + /*software reset, need to clear the set bit*/ + ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL); + ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1); + writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); + udelay(10); + ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1); + writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); + + /* reset the fifo */ + ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_FIFO_RESET_MASK, 1); + writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); +} + +static void imx8qxp_adc_reg_config(struct imx8qxp_adc *adc, int channel) +{ + u32 adc_cfg, adc_tctrl, adc_cmdl, adc_cmdh; + + /* ADC configuration */ + adc_cfg = FIELD_PREP(IMX8QXP_ADC_CFG_PWREN_MASK, 1) | + FIELD_PREP(IMX8QXP_ADC_CFG_PUDLY_MASK, 0x80)| + FIELD_PREP(IMX8QXP_ADC_CFG_REFSEL_MASK, 0) | + FIELD_PREP(IMX8QXP_ADC_CFG_PWRSEL_MASK, 3) | + FIELD_PREP(IMX8QXP_ADC_CFG_TPRICTRL_MASK, 0); + writel(adc_cfg, adc->regs + IMX8QXP_ADR_ADC_CFG); + + /* config the trigger control */ + adc_tctrl = FIELD_PREP(IMX8QXP_ADC_TCTRL_TCMD_MASK, 1) | + FIELD_PREP(IMX8QXP_ADC_TCTRL_TDLY_MASK, 0) | + FIELD_PREP(IMX8QXP_ADC_TCTRL_TPRI_MASK, IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH) | + FIELD_PREP(IMX8QXP_ADC_TCTRL_HTEN_MASK, IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS); + writel(adc_tctrl, adc->regs + IMX8QXP_ADR_ADC_TCTRL(0)); + + /* config the cmd */ + adc_cmdl = FIELD_PREP(IMX8QXP_ADC_CMDL_CSCALE_MASK, IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL) | + FIELD_PREP(IMX8QXP_ADC_CMDL_MODE_MASK, IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION) | + FIELD_PREP(IMX8QXP_ADC_CMDL_DIFF_MASK, IMX8QXP_ADC_CMDL_MODE_SINGLE) | + FIELD_PREP(IMX8QXP_ADC_CMDL_ABSEL_MASK, IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL) | + FIELD_PREP(IMX8QXP_ADC_CMDL_ADCH_MASK, channel); + writel(adc_cmdl, adc->regs + IMX8QXP_ADR_ADC_CMDL(0)); + + adc_cmdh = FIELD_PREP(IMX8QXP_ADC_CMDH_NEXT_MASK, 0) | + FIELD_PREP(IMX8QXP_ADC_CMDH_LOOP_MASK, 0) | + FIELD_PREP(IMX8QXP_ADC_CMDH_AVGS_MASK, 7) | + FIELD_PREP(IMX8QXP_ADC_CMDH_STS_MASK, 0) | + FIELD_PREP(IMX8QXP_ADC_CMDH_LWI_MASK, IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS) | + FIELD_PREP(IMX8QXP_ADC_CMDH_CMPEN_MASK, IMX8QXP_ADC_CMDH_CMPEN_DIS); + writel(adc_cmdh, adc->regs + IMX8QXP_ADR_ADC_CMDH(0)); +} + +static void imx8qxp_adc_fifo_config(struct imx8qxp_adc *adc) +{ + u32 fifo_ctrl, interrupt_en; + + fifo_ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL); + fifo_ctrl &= ~IMX8QXP_ADC_FCTRL_FWMARK_MASK; + /* set the watermark level to 1 */ + fifo_ctrl |= FIELD_PREP(IMX8QXP_ADC_FCTRL_FWMARK_MASK, 0); + writel(fifo_ctrl, adc->regs + IMX8QXP_ADR_ADC_FCTRL); + + /* FIFO Watermark Interrupt Enable */ + interrupt_en = readl(adc->regs + IMX8QXP_ADR_ADC_IE); + interrupt_en |= FIELD_PREP(IMX8QXP_ADC_IE_FWMIE_MASK, 1); + writel(interrupt_en, adc->regs + IMX8QXP_ADR_ADC_IE); +} + +static void imx8qxp_adc_disable(struct imx8qxp_adc *adc) +{ + u32 ctrl; + + ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL); + ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1); + writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); +} + +static int imx8qxp_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct imx8qxp_adc *adc = iio_priv(indio_dev); + struct device *dev = adc->dev; + + u32 ctrl, vref_uv; + long ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + pm_runtime_get_sync(dev); + + mutex_lock(&adc->lock); + reinit_completion(&adc->completion); + + imx8qxp_adc_reg_config(adc, chan->channel); + + imx8qxp_adc_fifo_config(adc); + + /* adc enable */ + ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL); + ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1); + writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); + /* adc start */ + writel(1, adc->regs + IMX8QXP_ADR_ADC_SWTRIG); + + ret = wait_for_completion_interruptible_timeout(&adc->completion, + IMX8QXP_ADC_TIMEOUT); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_sync_autosuspend(dev); + + if (ret == 0) { + mutex_unlock(&adc->lock); + return -ETIMEDOUT; + } + if (ret < 0) { + mutex_unlock(&adc->lock); + return ret; + } + + *val = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK, + readl(adc->regs + IMX8QXP_ADR_ADC_RESFIFO)); + + mutex_unlock(&adc->lock); + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + vref_uv = regulator_get_voltage(adc->vref); + *val = vref_uv / 1000; + *val2 = 12; + return IIO_VAL_FRACTIONAL_LOG2; + + case IIO_CHAN_INFO_SAMP_FREQ: + *val = clk_get_rate(adc->clk) / 3; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + +static irqreturn_t imx8qxp_adc_isr(int irq, void *dev_id) +{ + struct imx8qxp_adc *adc = dev_id; + u32 fifo_count; + + fifo_count = FIELD_GET(IMX8QXP_ADC_FCTRL_FCOUNT_MASK, + readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL)); + + if (fifo_count) + complete(&adc->completion); + + return IRQ_HANDLED; +} + +static int imx8qxp_adc_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct imx8qxp_adc *adc = iio_priv(indio_dev); + struct device *dev = adc->dev; + + if (!readval || reg % 4 || reg > IMX8QXP_ADR_ADC_TST) + return -EINVAL; + + pm_runtime_get_sync(dev); + + *readval = readl(adc->regs + reg); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_sync_autosuspend(dev); + + return 0; +} + +static const struct iio_info imx8qxp_adc_iio_info = { + .read_raw = &imx8qxp_adc_read_raw, + .debugfs_reg_access = &imx8qxp_adc_reg_access, +}; + +static int imx8qxp_adc_probe(struct platform_device *pdev) +{ + struct imx8qxp_adc *adc; + struct iio_dev *indio_dev; + struct device *dev = &pdev->dev; + int irq; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) { + dev_err(dev, "Failed allocating iio device\n"); + return -ENOMEM; + } + + adc = iio_priv(indio_dev); + adc->dev = dev; + + mutex_init(&adc->lock); + adc->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(adc->regs)) + return PTR_ERR(adc->regs); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + adc->clk = devm_clk_get(dev, "per"); + if (IS_ERR(adc->clk)) + return dev_err_probe(dev, PTR_ERR(adc->clk), "Failed getting clock\n"); + + adc->ipg_clk = devm_clk_get(dev, "ipg"); + if (IS_ERR(adc->ipg_clk)) + return dev_err_probe(dev, PTR_ERR(adc->ipg_clk), "Failed getting clock\n"); + + adc->vref = devm_regulator_get(dev, "vref"); + if (IS_ERR(adc->vref)) + return dev_err_probe(dev, PTR_ERR(adc->vref), "Failed getting reference voltage\n"); + + ret = regulator_enable(adc->vref); + if (ret) { + dev_err(dev, "Can't enable adc reference top voltage\n"); + return ret; + } + + platform_set_drvdata(pdev, indio_dev); + + init_completion(&adc->completion); + + indio_dev->name = ADC_DRIVER_NAME; + indio_dev->info = &imx8qxp_adc_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = imx8qxp_adc_iio_channels; + indio_dev->num_channels = ARRAY_SIZE(imx8qxp_adc_iio_channels); + + ret = clk_prepare_enable(adc->clk); + if (ret) { + dev_err(&pdev->dev, "Could not prepare or enable the clock.\n"); + goto error_regulator_disable; + } + + ret = clk_prepare_enable(adc->ipg_clk); + if (ret) { + dev_err(&pdev->dev, "Could not prepare or enable the clock.\n"); + goto error_adc_clk_disable; + } + + ret = devm_request_irq(dev, irq, imx8qxp_adc_isr, 0, ADC_DRIVER_NAME, adc); + if (ret < 0) { + dev_err(dev, "Failed requesting irq, irq = %d\n", irq); + goto error_ipg_clk_disable; + } + + imx8qxp_adc_reset(adc); + + ret = iio_device_register(indio_dev); + if (ret) { + imx8qxp_adc_disable(adc); + dev_err(dev, "Couldn't register the device.\n"); + goto error_ipg_clk_disable; + } + + pm_runtime_set_active(dev); + pm_runtime_set_autosuspend_delay(dev, 50); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); + + return 0; + +error_ipg_clk_disable: + clk_disable_unprepare(adc->ipg_clk); +error_adc_clk_disable: + clk_disable_unprepare(adc->clk); +error_regulator_disable: + regulator_disable(adc->vref); + + return ret; +} + +static int imx8qxp_adc_remove(struct platform_device *pdev) +{ + struct iio_dev *indio_dev = platform_get_drvdata(pdev); + struct imx8qxp_adc *adc = iio_priv(indio_dev); + struct device *dev = adc->dev; + + pm_runtime_get_sync(dev); + + iio_device_unregister(indio_dev); + + imx8qxp_adc_disable(adc); + + clk_disable_unprepare(adc->clk); + clk_disable_unprepare(adc->ipg_clk); + regulator_disable(adc->vref); + + pm_runtime_disable(dev); + pm_runtime_put_noidle(dev); + + return 0; +} + +static __maybe_unused int imx8qxp_adc_runtime_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct imx8qxp_adc *adc = iio_priv(indio_dev); + + imx8qxp_adc_disable(adc); + + clk_disable_unprepare(adc->clk); + clk_disable_unprepare(adc->ipg_clk); + regulator_disable(adc->vref); + + return 0; +} + +static __maybe_unused int imx8qxp_adc_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct imx8qxp_adc *adc = iio_priv(indio_dev); + int ret; + + ret = regulator_enable(adc->vref); + if (ret) { + dev_err(dev, "Can't enable adc reference top voltage, err = %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(adc->clk); + if (ret) { + dev_err(dev, "Could not prepare or enable clock.\n"); + goto err_disable_reg; + } + + ret = clk_prepare_enable(adc->ipg_clk); + if (ret) { + dev_err(dev, "Could not prepare or enable clock.\n"); + goto err_unprepare_clk; + } + + imx8qxp_adc_reset(adc); + + return 0; + +err_unprepare_clk: + clk_disable_unprepare(adc->clk); + +err_disable_reg: + regulator_disable(adc->vref); + + return ret; +} + +static const struct dev_pm_ops imx8qxp_adc_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(imx8qxp_adc_runtime_suspend, imx8qxp_adc_runtime_resume, NULL) +}; + +static const struct of_device_id imx8qxp_adc_match[] = { + { .compatible = "nxp,imx8qxp-adc", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qxp_adc_match); + +static struct platform_driver imx8qxp_adc_driver = { + .probe = imx8qxp_adc_probe, + .remove = imx8qxp_adc_remove, + .driver = { + .name = ADC_DRIVER_NAME, + .of_match_table = imx8qxp_adc_match, + .pm = &imx8qxp_adc_pm_ops, + }, +}; + +module_platform_driver(imx8qxp_adc_driver); + +MODULE_DESCRIPTION("i.MX8QuadXPlus ADC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/adc/intel_mrfld_adc.c b/drivers/iio/adc/intel_mrfld_adc.c index 75394350eb4c..616de0c3a049 100644 --- a/drivers/iio/adc/intel_mrfld_adc.c +++ b/drivers/iio/adc/intel_mrfld_adc.c @@ -205,8 +205,6 @@ static int mrfld_adc_probe(struct platform_device *pdev) if (ret) return ret; - platform_set_drvdata(pdev, indio_dev); - indio_dev->name = pdev->name; indio_dev->channels = mrfld_adc_channels; @@ -214,28 +212,11 @@ static int mrfld_adc_probe(struct platform_device *pdev) indio_dev->info = &mrfld_adc_iio_info; indio_dev->modes = INDIO_DIRECT_MODE; - ret = iio_map_array_register(indio_dev, iio_maps); + ret = devm_iio_map_array_register(dev, indio_dev, iio_maps); if (ret) return ret; - ret = devm_iio_device_register(dev, indio_dev); - if (ret < 0) - goto err_array_unregister; - - return 0; - -err_array_unregister: - iio_map_array_unregister(indio_dev); - return ret; -} - -static int mrfld_adc_remove(struct platform_device *pdev) -{ - struct iio_dev *indio_dev = platform_get_drvdata(pdev); - - iio_map_array_unregister(indio_dev); - - return 0; + return devm_iio_device_register(dev, indio_dev); } static const struct platform_device_id mrfld_adc_id_table[] = { @@ -249,7 +230,6 @@ static struct platform_driver mrfld_adc_driver = { .name = "mrfld_bcove_adc", }, .probe = mrfld_adc_probe, - .remove = mrfld_adc_remove, .id_table = mrfld_adc_id_table, }; module_platform_driver(mrfld_adc_driver); diff --git a/drivers/iio/adc/lp8788_adc.c b/drivers/iio/adc/lp8788_adc.c index 8fb57e375529..6d9b354bc705 100644 --- a/drivers/iio/adc/lp8788_adc.c +++ b/drivers/iio/adc/lp8788_adc.c @@ -163,7 +163,8 @@ static struct iio_map lp8788_default_iio_maps[] = { { } }; -static int lp8788_iio_map_register(struct iio_dev *indio_dev, +static int lp8788_iio_map_register(struct device *dev, + struct iio_dev *indio_dev, struct lp8788_platform_data *pdata, struct lp8788_adc *adc) { @@ -173,7 +174,7 @@ static int lp8788_iio_map_register(struct iio_dev *indio_dev, map = (!pdata || !pdata->adc_pdata) ? lp8788_default_iio_maps : pdata->adc_pdata; - ret = iio_map_array_register(indio_dev, map); + ret = devm_iio_map_array_register(dev, indio_dev, map); if (ret) { dev_err(&indio_dev->dev, "iio map err: %d\n", ret); return ret; @@ -196,9 +197,8 @@ static int lp8788_adc_probe(struct platform_device *pdev) adc = iio_priv(indio_dev); adc->lp = lp; - platform_set_drvdata(pdev, indio_dev); - ret = lp8788_iio_map_register(indio_dev, lp->pdata, adc); + ret = lp8788_iio_map_register(&pdev->dev, indio_dev, lp->pdata, adc); if (ret) return ret; @@ -210,32 +210,11 @@ static int lp8788_adc_probe(struct platform_device *pdev) indio_dev->channels = lp8788_adc_channels; indio_dev->num_channels = ARRAY_SIZE(lp8788_adc_channels); - ret = iio_device_register(indio_dev); - if (ret) { - dev_err(&pdev->dev, "iio dev register err: %d\n", ret); - goto err_iio_device; - } - - return 0; - -err_iio_device: - iio_map_array_unregister(indio_dev); - return ret; -} - -static int lp8788_adc_remove(struct platform_device *pdev) -{ - struct iio_dev *indio_dev = platform_get_drvdata(pdev); - - iio_device_unregister(indio_dev); - iio_map_array_unregister(indio_dev); - - return 0; + return devm_iio_device_register(&pdev->dev, indio_dev); } static struct platform_driver lp8788_adc_driver = { .probe = lp8788_adc_probe, - .remove = lp8788_adc_remove, .driver = { .name = LP8788_DEV_ADC, }, diff --git a/drivers/iio/adc/lpc18xx_adc.c b/drivers/iio/adc/lpc18xx_adc.c index 3566990ae87d..ceefa4d793cf 100644 --- a/drivers/iio/adc/lpc18xx_adc.c +++ b/drivers/iio/adc/lpc18xx_adc.c @@ -115,6 +115,23 @@ static const struct iio_info lpc18xx_adc_info = { .read_raw = lpc18xx_adc_read_raw, }; +static void lpc18xx_clear_cr_reg(void *data) +{ + struct lpc18xx_adc *adc = data; + + writel(0, adc->base + LPC18XX_ADC_CR); +} + +static void lpc18xx_clk_disable(void *clk) +{ + clk_disable_unprepare(clk); +} + +static void lpc18xx_regulator_disable(void *vref) +{ + regulator_disable(vref); +} + static int lpc18xx_adc_probe(struct platform_device *pdev) { struct iio_dev *indio_dev; @@ -127,7 +144,6 @@ static int lpc18xx_adc_probe(struct platform_device *pdev) if (!indio_dev) return -ENOMEM; - platform_set_drvdata(pdev, indio_dev); adc = iio_priv(indio_dev); adc->dev = &pdev->dev; mutex_init(&adc->lock); @@ -137,19 +153,17 @@ static int lpc18xx_adc_probe(struct platform_device *pdev) return PTR_ERR(adc->base); adc->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(adc->clk)) { - dev_err(&pdev->dev, "error getting clock\n"); - return PTR_ERR(adc->clk); - } + if (IS_ERR(adc->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(adc->clk), + "error getting clock\n"); rate = clk_get_rate(adc->clk); clkdiv = DIV_ROUND_UP(rate, LPC18XX_ADC_CLK_TARGET); adc->vref = devm_regulator_get(&pdev->dev, "vref"); - if (IS_ERR(adc->vref)) { - dev_err(&pdev->dev, "error getting regulator\n"); - return PTR_ERR(adc->vref); - } + if (IS_ERR(adc->vref)) + return dev_err_probe(&pdev->dev, PTR_ERR(adc->vref), + "error getting regulator\n"); indio_dev->name = dev_name(&pdev->dev); indio_dev->info = &lpc18xx_adc_info; @@ -163,44 +177,30 @@ static int lpc18xx_adc_probe(struct platform_device *pdev) return ret; } + ret = devm_add_action_or_reset(&pdev->dev, lpc18xx_regulator_disable, adc->vref); + if (ret) + return ret; + ret = clk_prepare_enable(adc->clk); if (ret) { dev_err(&pdev->dev, "unable to enable clock\n"); - goto dis_reg; + return ret; } + ret = devm_add_action_or_reset(&pdev->dev, lpc18xx_clk_disable, + adc->clk); + if (ret) + return ret; + adc->cr_reg = (clkdiv << LPC18XX_ADC_CR_CLKDIV_SHIFT) | LPC18XX_ADC_CR_PDN; writel(adc->cr_reg, adc->base + LPC18XX_ADC_CR); - ret = iio_device_register(indio_dev); - if (ret) { - dev_err(&pdev->dev, "unable to register device\n"); - goto dis_clk; - } - - return 0; - -dis_clk: - writel(0, adc->base + LPC18XX_ADC_CR); - clk_disable_unprepare(adc->clk); -dis_reg: - regulator_disable(adc->vref); - return ret; -} - -static int lpc18xx_adc_remove(struct platform_device *pdev) -{ - struct iio_dev *indio_dev = platform_get_drvdata(pdev); - struct lpc18xx_adc *adc = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - - writel(0, adc->base + LPC18XX_ADC_CR); - clk_disable_unprepare(adc->clk); - regulator_disable(adc->vref); + ret = devm_add_action_or_reset(&pdev->dev, lpc18xx_clear_cr_reg, adc); + if (ret) + return ret; - return 0; + return devm_iio_device_register(&pdev->dev, indio_dev); } static const struct of_device_id lpc18xx_adc_match[] = { @@ -211,7 +211,6 @@ MODULE_DEVICE_TABLE(of, lpc18xx_adc_match); static struct platform_driver lpc18xx_adc_driver = { .probe = lpc18xx_adc_probe, - .remove = lpc18xx_adc_remove, .driver = { .name = "lpc18xx-adc", .of_match_table = lpc18xx_adc_match, diff --git a/drivers/iio/adc/max1027.c b/drivers/iio/adc/max1027.c index 655ab02d03d8..4daf1d576c4e 100644 --- a/drivers/iio/adc/max1027.c +++ b/drivers/iio/adc/max1027.c @@ -60,6 +60,9 @@ #define MAX1027_NAVG_32 (0x03 << 2) #define MAX1027_AVG_EN BIT(4) +/* Device can achieve 300ksps so we assume a 3.33us conversion delay */ +#define MAX1027_CONVERSION_UDELAY 4 + enum max1027_id { max1027, max1029, @@ -103,7 +106,7 @@ MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids); .sign = 'u', \ .realbits = depth, \ .storagebits = 16, \ - .shift = 2, \ + .shift = (depth == 10) ? 2 : 0, \ .endianness = IIO_BE, \ }, \ } @@ -142,7 +145,6 @@ MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids); MAX1027_V_CHAN(11, depth) #define MAX1X31_CHANNELS(depth) \ - MAX1X27_CHANNELS(depth), \ MAX1X29_CHANNELS(depth), \ MAX1027_V_CHAN(12, depth), \ MAX1027_V_CHAN(13, depth), \ @@ -173,18 +175,53 @@ static const struct iio_chan_spec max1231_channels[] = { MAX1X31_CHANNELS(12), }; +/* + * These devices are able to scan from 0 to N, N being the highest voltage + * channel requested by the user. The temperature can be included or not, + * but cannot be retrieved alone. Based on the below + * ->available_scan_masks, the core will select the most appropriate + * ->active_scan_mask and the "minimum" number of channels will be + * scanned and pushed to the buffers. + * + * For example, if the user wants channels 1, 4 and 5, all channels from + * 0 to 5 will be scanned and pushed to the IIO buffers. The core will then + * filter out the unneeded samples based on the ->active_scan_mask that has + * been selected and only channels 1, 4 and 5 will be available to the user + * in the shared buffer. + */ +#define MAX1X27_SCAN_MASK_TEMP BIT(0) + +#define MAX1X27_SCAN_MASKS(temp) \ + GENMASK(1, 1 - (temp)), GENMASK(2, 1 - (temp)), \ + GENMASK(3, 1 - (temp)), GENMASK(4, 1 - (temp)), \ + GENMASK(5, 1 - (temp)), GENMASK(6, 1 - (temp)), \ + GENMASK(7, 1 - (temp)), GENMASK(8, 1 - (temp)) + +#define MAX1X29_SCAN_MASKS(temp) \ + MAX1X27_SCAN_MASKS(temp), \ + GENMASK(9, 1 - (temp)), GENMASK(10, 1 - (temp)), \ + GENMASK(11, 1 - (temp)), GENMASK(12, 1 - (temp)) + +#define MAX1X31_SCAN_MASKS(temp) \ + MAX1X29_SCAN_MASKS(temp), \ + GENMASK(13, 1 - (temp)), GENMASK(14, 1 - (temp)), \ + GENMASK(15, 1 - (temp)), GENMASK(16, 1 - (temp)) + static const unsigned long max1027_available_scan_masks[] = { - 0x000001ff, + MAX1X27_SCAN_MASKS(0), + MAX1X27_SCAN_MASKS(1), 0x00000000, }; static const unsigned long max1029_available_scan_masks[] = { - 0x00001fff, + MAX1X29_SCAN_MASKS(0), + MAX1X29_SCAN_MASKS(1), 0x00000000, }; static const unsigned long max1031_available_scan_masks[] = { - 0x0001ffff, + MAX1X31_SCAN_MASKS(0), + MAX1X31_SCAN_MASKS(1), 0x00000000, }; @@ -233,10 +270,65 @@ struct max1027_state { struct iio_trigger *trig; __be16 *buffer; struct mutex lock; + struct completion complete; u8 reg ____cacheline_aligned; }; +static int max1027_wait_eoc(struct iio_dev *indio_dev) +{ + struct max1027_state *st = iio_priv(indio_dev); + unsigned int conversion_time = MAX1027_CONVERSION_UDELAY; + int ret; + + if (st->spi->irq) { + ret = wait_for_completion_timeout(&st->complete, + msecs_to_jiffies(1000)); + reinit_completion(&st->complete); + if (!ret) + return -ETIMEDOUT; + } else { + if (indio_dev->active_scan_mask) + conversion_time *= hweight32(*indio_dev->active_scan_mask); + + usleep_range(conversion_time, conversion_time * 2); + } + + return 0; +} + +/* Scan from chan 0 to the highest requested channel. Include temperature on demand. */ +static int max1027_configure_chans_and_start(struct iio_dev *indio_dev) +{ + struct max1027_state *st = iio_priv(indio_dev); + + st->reg = MAX1027_CONV_REG | MAX1027_SCAN_0_N; + st->reg |= MAX1027_CHAN(fls(*indio_dev->active_scan_mask) - 2); + if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP) + st->reg |= MAX1027_TEMP; + + return spi_write(st->spi, &st->reg, 1); +} + +static int max1027_enable_trigger(struct iio_dev *indio_dev, bool enable) +{ + struct max1027_state *st = iio_priv(indio_dev); + + st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2; + + /* + * Start acquisition on: + * MODE0: external hardware trigger wired to the cnvst input pin + * MODE2: conversion register write + */ + if (enable) + st->reg |= MAX1027_CKS_MODE0; + else + st->reg |= MAX1027_CKS_MODE2; + + return spi_write(st->spi, &st->reg, 1); +} + static int max1027_read_single_value(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) @@ -244,19 +336,9 @@ static int max1027_read_single_value(struct iio_dev *indio_dev, int ret; struct max1027_state *st = iio_priv(indio_dev); - if (iio_buffer_enabled(indio_dev)) { - dev_warn(&indio_dev->dev, "trigger mode already enabled"); - return -EBUSY; - } - - /* Start acquisition on conversion register write */ - st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2; - ret = spi_write(st->spi, &st->reg, 1); - if (ret < 0) { - dev_err(&indio_dev->dev, - "Failed to configure setup register\n"); + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) return ret; - } /* Configure conversion register with the requested chan */ st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) | @@ -267,18 +349,24 @@ static int max1027_read_single_value(struct iio_dev *indio_dev, if (ret < 0) { dev_err(&indio_dev->dev, "Failed to configure conversion register\n"); + iio_device_release_direct_mode(indio_dev); return ret; } /* * For an unknown reason, when we use the mode "10" (write * conversion register), the interrupt doesn't occur every time. - * So we just wait 1 ms. + * So we just wait the maximum conversion time and deliver the value. */ - mdelay(1); + ret = max1027_wait_eoc(indio_dev); + if (ret) + return ret; /* Read result */ ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2); + + iio_device_release_direct_mode(indio_dev); + if (ret < 0) return ret; @@ -328,8 +416,8 @@ static int max1027_read_raw(struct iio_dev *indio_dev, } static int max1027_debugfs_reg_access(struct iio_dev *indio_dev, - unsigned reg, unsigned writeval, - unsigned *readval) + unsigned int reg, unsigned int writeval, + unsigned int *readval) { struct max1027_state *st = iio_priv(indio_dev); u8 *val = (u8 *)st->buffer; @@ -344,61 +432,96 @@ static int max1027_debugfs_reg_access(struct iio_dev *indio_dev, return spi_write(st->spi, val, 1); } -static int max1027_validate_trigger(struct iio_dev *indio_dev, - struct iio_trigger *trig) +static int max1027_set_cnvst_trigger_state(struct iio_trigger *trig, bool state) { - struct max1027_state *st = iio_priv(indio_dev); + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); + int ret; - if (st->trig != trig) - return -EINVAL; + /* + * In order to disable the convst trigger, start acquisition on + * conversion register write, which basically disables triggering + * conversions upon cnvst changes and thus has the effect of disabling + * the external hardware trigger. + */ + ret = max1027_enable_trigger(indio_dev, state); + if (ret) + return ret; + + if (state) { + ret = max1027_configure_chans_and_start(indio_dev); + if (ret) + return ret; + } return 0; } -static int max1027_set_trigger_state(struct iio_trigger *trig, bool state) +static int max1027_read_scan(struct iio_dev *indio_dev) { - struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); struct max1027_state *st = iio_priv(indio_dev); + unsigned int scanned_chans; int ret; - if (state) { - /* Start acquisition on cnvst */ - st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 | - MAX1027_REF_MODE2; - ret = spi_write(st->spi, &st->reg, 1); - if (ret < 0) - return ret; + scanned_chans = fls(*indio_dev->active_scan_mask) - 1; + if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP) + scanned_chans++; - /* Scan from 0 to max */ - st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) | - MAX1027_SCAN_N_M | MAX1027_TEMP; - ret = spi_write(st->spi, &st->reg, 1); - if (ret < 0) - return ret; - } else { - /* Start acquisition on conversion register write */ - st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 | - MAX1027_REF_MODE2; - ret = spi_write(st->spi, &st->reg, 1); - if (ret < 0) - return ret; - } + /* fill buffer with all channel */ + ret = spi_read(st->spi, st->buffer, scanned_chans * 2); + if (ret < 0) + return ret; + + iio_push_to_buffers(indio_dev, st->buffer); return 0; } +static irqreturn_t max1027_handler(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct max1027_state *st = iio_priv(indio_dev); + + /* + * If buffers are disabled (raw read) or when using external triggers, + * we just need to unlock the waiters which will then handle the data. + * + * When using the internal trigger, we must hand-off the choice of the + * handler to the core which will then lookup through the interrupt tree + * for the right handler registered with iio_triggered_buffer_setup() + * to execute, as this trigger might very well be used in conjunction + * with another device. The core will then call the relevant handler to + * perform the data processing step. + */ + if (!iio_buffer_enabled(indio_dev)) + complete(&st->complete); + else + iio_trigger_poll(indio_dev->trig); + + return IRQ_HANDLED; +} + static irqreturn_t max1027_trigger_handler(int irq, void *private) { struct iio_poll_func *pf = private; struct iio_dev *indio_dev = pf->indio_dev; - struct max1027_state *st = iio_priv(indio_dev); + int ret; - pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private); + if (!iio_trigger_using_own(indio_dev)) { + ret = max1027_configure_chans_and_start(indio_dev); + if (ret) + goto out; - /* fill buffer with all channel */ - spi_read(st->spi, st->buffer, indio_dev->masklength * 2); + /* This is a threaded handler, it is fine to wait for an IRQ */ + ret = max1027_wait_eoc(indio_dev); + if (ret) + goto out; + } - iio_push_to_buffers(indio_dev, st->buffer); + ret = max1027_read_scan(indio_dev); +out: + if (ret) + dev_err(&indio_dev->dev, + "Cannot read scanned values (%d)\n", ret); iio_trigger_notify_done(indio_dev->trig); @@ -407,12 +530,11 @@ static irqreturn_t max1027_trigger_handler(int irq, void *private) static const struct iio_trigger_ops max1027_trigger_ops = { .validate_device = &iio_trigger_validate_own_device, - .set_trigger_state = &max1027_set_trigger_state, + .set_trigger_state = &max1027_set_cnvst_trigger_state, }; static const struct iio_info max1027_info = { .read_raw = &max1027_read_raw, - .validate_trigger = &max1027_validate_trigger, .debugfs_reg_access = &max1027_debugfs_reg_access, }; @@ -422,10 +544,8 @@ static int max1027_probe(struct spi_device *spi) struct iio_dev *indio_dev; struct max1027_state *st; - pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi); - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); - if (indio_dev == NULL) { + if (!indio_dev) { pr_err("Can't allocate iio device\n"); return -ENOMEM; } @@ -435,6 +555,7 @@ static int max1027_probe(struct spi_device *spi) st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data]; mutex_init(&st->lock); + init_completion(&st->complete); indio_dev->name = spi_get_device_id(spi)->name; indio_dev->info = &max1027_info; @@ -444,26 +565,26 @@ static int max1027_probe(struct spi_device *spi) indio_dev->available_scan_masks = st->info->available_scan_masks; st->buffer = devm_kmalloc_array(&indio_dev->dev, - indio_dev->num_channels, 2, - GFP_KERNEL); - if (st->buffer == NULL) { - dev_err(&indio_dev->dev, "Can't allocate buffer\n"); + indio_dev->num_channels, 2, + GFP_KERNEL); + if (!st->buffer) return -ENOMEM; + + /* Enable triggered buffers */ + ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, + &iio_pollfunc_store_time, + &max1027_trigger_handler, + NULL); + if (ret < 0) { + dev_err(&indio_dev->dev, "Failed to setup buffer\n"); + return ret; } + /* If there is an EOC interrupt, register the cnvst hardware trigger */ if (spi->irq) { - ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, - &iio_pollfunc_store_time, - &max1027_trigger_handler, - NULL); - if (ret < 0) { - dev_err(&indio_dev->dev, "Failed to setup buffer\n"); - return ret; - } - st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger", indio_dev->name); - if (st->trig == NULL) { + if (!st->trig) { ret = -ENOMEM; dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n"); @@ -480,12 +601,9 @@ static int max1027_probe(struct spi_device *spi) return ret; } - ret = devm_request_threaded_irq(&spi->dev, spi->irq, - iio_trigger_generic_data_rdy_poll, - NULL, - IRQF_TRIGGER_FALLING, - spi->dev.driver->name, - st->trig); + ret = devm_request_irq(&spi->dev, spi->irq, max1027_handler, + IRQF_TRIGGER_FALLING, + spi->dev.driver->name, indio_dev); if (ret < 0) { dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n"); return ret; @@ -508,6 +626,11 @@ static int max1027_probe(struct spi_device *spi) return ret; } + /* Assume conversion on register write for now */ + ret = max1027_enable_trigger(indio_dev, false); + if (ret) + return ret; + return devm_iio_device_register(&spi->dev, indio_dev); } diff --git a/drivers/iio/adc/max1118.c b/drivers/iio/adc/max1118.c index 8cec9d949083..a41bc570be21 100644 --- a/drivers/iio/adc/max1118.c +++ b/drivers/iio/adc/max1118.c @@ -221,10 +221,9 @@ static int max1118_probe(struct spi_device *spi) if (id->driver_data == max1118) { adc->reg = devm_regulator_get(&spi->dev, "vref"); - if (IS_ERR(adc->reg)) { - dev_err(&spi->dev, "failed to get vref regulator\n"); - return PTR_ERR(adc->reg); - } + if (IS_ERR(adc->reg)) + return dev_err_probe(&spi->dev, PTR_ERR(adc->reg), + "failed to get vref regulator\n"); ret = regulator_enable(adc->reg); if (ret) return ret; diff --git a/drivers/iio/adc/max1241.c b/drivers/iio/adc/max1241.c index b60f8448f21a..a5afd84af58b 100644 --- a/drivers/iio/adc/max1241.c +++ b/drivers/iio/adc/max1241.c @@ -148,10 +148,9 @@ static int max1241_probe(struct spi_device *spi) mutex_init(&adc->lock); adc->vdd = devm_regulator_get(dev, "vdd"); - if (IS_ERR(adc->vdd)) { - dev_err(dev, "failed to get vdd regulator\n"); - return PTR_ERR(adc->vdd); - } + if (IS_ERR(adc->vdd)) + return dev_err_probe(dev, PTR_ERR(adc->vdd), + "failed to get vdd regulator\n"); ret = regulator_enable(adc->vdd); if (ret) @@ -164,10 +163,9 @@ static int max1241_probe(struct spi_device *spi) } adc->vref = devm_regulator_get(dev, "vref"); - if (IS_ERR(adc->vref)) { - dev_err(dev, "failed to get vref regulator\n"); - return PTR_ERR(adc->vref); - } + if (IS_ERR(adc->vref)) + return dev_err_probe(dev, PTR_ERR(adc->vref), + "failed to get vref regulator\n"); ret = regulator_enable(adc->vref); if (ret) @@ -182,7 +180,8 @@ static int max1241_probe(struct spi_device *spi) adc->shutdown = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); if (IS_ERR(adc->shutdown)) - return PTR_ERR(adc->shutdown); + return dev_err_probe(dev, PTR_ERR(adc->shutdown), + "cannot get shutdown gpio\n"); if (adc->shutdown) dev_dbg(dev, "shutdown pin passed, low-power mode enabled"); diff --git a/drivers/iio/adc/max1363.c b/drivers/iio/adc/max1363.c index f2b576c69949..eef55ed4814a 100644 --- a/drivers/iio/adc/max1363.c +++ b/drivers/iio/adc/max1363.c @@ -1577,6 +1577,11 @@ static const struct of_device_id max1363_of_match[] = { }; MODULE_DEVICE_TABLE(of, max1363_of_match); +static void max1363_reg_disable(void *reg) +{ + regulator_disable(reg); +} + static int max1363_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -1590,7 +1595,8 @@ static int max1363_probe(struct i2c_client *client, if (!indio_dev) return -ENOMEM; - ret = iio_map_array_register(indio_dev, client->dev.platform_data); + ret = devm_iio_map_array_register(&client->dev, indio_dev, + client->dev.platform_data); if (ret < 0) return ret; @@ -1598,17 +1604,16 @@ static int max1363_probe(struct i2c_client *client, mutex_init(&st->lock); st->reg = devm_regulator_get(&client->dev, "vcc"); - if (IS_ERR(st->reg)) { - ret = PTR_ERR(st->reg); - goto error_unregister_map; - } + if (IS_ERR(st->reg)) + return PTR_ERR(st->reg); ret = regulator_enable(st->reg); if (ret) - goto error_unregister_map; + return ret; - /* this is only used for device removal purposes */ - i2c_set_clientdata(client, indio_dev); + ret = devm_add_action_or_reset(&client->dev, max1363_reg_disable, st->reg); + if (ret) + return ret; st->chip_info = device_get_match_data(&client->dev); if (!st->chip_info) @@ -1622,13 +1627,17 @@ static int max1363_probe(struct i2c_client *client, ret = regulator_enable(vref); if (ret) - goto error_disable_reg; + return ret; + + ret = devm_add_action_or_reset(&client->dev, max1363_reg_disable, vref); + if (ret) + return ret; + st->vref = vref; vref_uv = regulator_get_voltage(vref); - if (vref_uv <= 0) { - ret = -EINVAL; - goto error_disable_reg; - } + if (vref_uv <= 0) + return -EINVAL; + st->vref_uv = vref_uv; } @@ -1640,13 +1649,12 @@ static int max1363_probe(struct i2c_client *client, st->send = max1363_smbus_send; st->recv = max1363_smbus_recv; } else { - ret = -EOPNOTSUPP; - goto error_disable_reg; + return -EOPNOTSUPP; } ret = max1363_alloc_scan_masks(indio_dev); if (ret) - goto error_disable_reg; + return ret; indio_dev->name = id->name; indio_dev->channels = st->chip_info->channels; @@ -1655,12 +1663,12 @@ static int max1363_probe(struct i2c_client *client, indio_dev->modes = INDIO_DIRECT_MODE; ret = max1363_initial_setup(st); if (ret < 0) - goto error_disable_reg; + return ret; - ret = iio_triggered_buffer_setup(indio_dev, NULL, - &max1363_trigger_handler, NULL); + ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL, + &max1363_trigger_handler, NULL); if (ret) - goto error_disable_reg; + return ret; if (client->irq) { ret = devm_request_threaded_irq(&client->dev, st->client->irq, @@ -1671,39 +1679,10 @@ static int max1363_probe(struct i2c_client *client, indio_dev); if (ret) - goto error_uninit_buffer; + return ret; } - ret = iio_device_register(indio_dev); - if (ret < 0) - goto error_uninit_buffer; - - return 0; - -error_uninit_buffer: - iio_triggered_buffer_cleanup(indio_dev); -error_disable_reg: - if (st->vref) - regulator_disable(st->vref); - regulator_disable(st->reg); -error_unregister_map: - iio_map_array_unregister(indio_dev); - return ret; -} - -static int max1363_remove(struct i2c_client *client) -{ - struct iio_dev *indio_dev = i2c_get_clientdata(client); - struct max1363_state *st = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - iio_triggered_buffer_cleanup(indio_dev); - if (st->vref) - regulator_disable(st->vref); - regulator_disable(st->reg); - iio_map_array_unregister(indio_dev); - - return 0; + return devm_iio_device_register(&client->dev, indio_dev); } static const struct i2c_device_id max1363_id[] = { @@ -1756,7 +1735,6 @@ static struct i2c_driver max1363_driver = { .of_match_table = max1363_of_match, }, .probe = max1363_probe, - .remove = max1363_remove, .id_table = max1363_id, }; module_i2c_driver(max1363_driver); diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 705d5e11a54b..62cc6fb0ef85 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -1230,35 +1230,31 @@ static int meson_sar_adc_probe(struct platform_device *pdev) return ret; priv->clkin = devm_clk_get(&pdev->dev, "clkin"); - if (IS_ERR(priv->clkin)) { - dev_err(&pdev->dev, "failed to get clkin\n"); - return PTR_ERR(priv->clkin); - } + if (IS_ERR(priv->clkin)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkin), + "failed to get clkin\n"); priv->core_clk = devm_clk_get(&pdev->dev, "core"); - if (IS_ERR(priv->core_clk)) { - dev_err(&pdev->dev, "failed to get core clk\n"); - return PTR_ERR(priv->core_clk); - } + if (IS_ERR(priv->core_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->core_clk), + "failed to get core clk\n"); priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk"); if (IS_ERR(priv->adc_clk)) { - if (PTR_ERR(priv->adc_clk) == -ENOENT) { + if (PTR_ERR(priv->adc_clk) == -ENOENT) priv->adc_clk = NULL; - } else { - dev_err(&pdev->dev, "failed to get adc clk\n"); - return PTR_ERR(priv->adc_clk); - } + else + return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_clk), + "failed to get adc clk\n"); } priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel"); if (IS_ERR(priv->adc_sel_clk)) { - if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) { + if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) priv->adc_sel_clk = NULL; - } else { - dev_err(&pdev->dev, "failed to get adc_sel clk\n"); - return PTR_ERR(priv->adc_sel_clk); - } + else + return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_sel_clk), + "failed to get adc_sel clk\n"); } /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ @@ -1269,10 +1265,9 @@ static int meson_sar_adc_probe(struct platform_device *pdev) } priv->vref = devm_regulator_get(&pdev->dev, "vref"); - if (IS_ERR(priv->vref)) { - dev_err(&pdev->dev, "failed to get vref regulator\n"); - return PTR_ERR(priv->vref); - } + if (IS_ERR(priv->vref)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), + "failed to get vref regulator\n"); priv->calibscale = MILLION; diff --git a/drivers/iio/adc/mt6577_auxadc.c b/drivers/iio/adc/mt6577_auxadc.c index 79c1dd68b909..d4fccd52ef08 100644 --- a/drivers/iio/adc/mt6577_auxadc.c +++ b/drivers/iio/adc/mt6577_auxadc.c @@ -82,6 +82,10 @@ static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = { MT6577_AUXADC_CHANNEL(15), }; +/* For Voltage calculation */ +#define VOLTAGE_FULL_RANGE 1500 /* VA voltage */ +#define AUXADC_PRECISE 4096 /* 12 bits */ + static int mt_auxadc_get_cali_data(int rawdata, bool enable_cali) { return rawdata; @@ -191,6 +195,10 @@ static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev, } if (adc_dev->dev_comp->sample_data_cali) *val = mt_auxadc_get_cali_data(*val, true); + + /* Convert adc raw data to voltage: 0 - 1500 mV */ + *val = *val * VOLTAGE_FULL_RANGE / AUXADC_PRECISE; + return IIO_VAL_INT; default: diff --git a/drivers/iio/adc/nau7802.c b/drivers/iio/adc/nau7802.c index bb70b51d25b1..976c235f3079 100644 --- a/drivers/iio/adc/nau7802.c +++ b/drivers/iio/adc/nau7802.c @@ -428,8 +428,6 @@ static int nau7802_probe(struct i2c_client *client, st = iio_priv(indio_dev); - i2c_set_clientdata(client, indio_dev); - indio_dev->name = dev_name(&client->dev); indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &nau7802_info; @@ -495,13 +493,13 @@ static int nau7802_probe(struct i2c_client *client, * will enable them back when we will need them.. */ if (client->irq) { - ret = request_threaded_irq(client->irq, - NULL, - nau7802_eoc_trigger, - IRQF_TRIGGER_HIGH | IRQF_ONESHOT | - IRQF_NO_AUTOEN, - client->dev.driver->name, - indio_dev); + ret = devm_request_threaded_irq(&client->dev, client->irq, + NULL, + nau7802_eoc_trigger, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT | + IRQF_NO_AUTOEN, + client->dev.driver->name, + indio_dev); if (ret) { /* * What may happen here is that our IRQ controller is @@ -526,7 +524,7 @@ static int nau7802_probe(struct i2c_client *client, ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2, NAU7802_CTRL2_CRS(st->sample_rate)); if (ret) - goto error_free_irq; + return ret; } /* Setup the ADC channels available on the board */ @@ -536,36 +534,7 @@ static int nau7802_probe(struct i2c_client *client, mutex_init(&st->lock); mutex_init(&st->data_lock); - ret = iio_device_register(indio_dev); - if (ret < 0) { - dev_err(&client->dev, "Couldn't register the device.\n"); - goto error_device_register; - } - - return 0; - -error_device_register: - mutex_destroy(&st->lock); - mutex_destroy(&st->data_lock); -error_free_irq: - if (client->irq) - free_irq(client->irq, indio_dev); - - return ret; -} - -static int nau7802_remove(struct i2c_client *client) -{ - struct iio_dev *indio_dev = i2c_get_clientdata(client); - struct nau7802_state *st = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - mutex_destroy(&st->lock); - mutex_destroy(&st->data_lock); - if (client->irq) - free_irq(client->irq, indio_dev); - - return 0; + return devm_iio_device_register(&client->dev, indio_dev); } static const struct i2c_device_id nau7802_i2c_id[] = { @@ -582,7 +551,6 @@ MODULE_DEVICE_TABLE(of, nau7802_dt_ids); static struct i2c_driver nau7802_driver = { .probe = nau7802_probe, - .remove = nau7802_remove, .id_table = nau7802_i2c_id, .driver = { .name = "nau7802", diff --git a/drivers/iio/adc/qcom-pm8xxx-xoadc.c b/drivers/iio/adc/qcom-pm8xxx-xoadc.c index 0610bf254771..21d7eff645c3 100644 --- a/drivers/iio/adc/qcom-pm8xxx-xoadc.c +++ b/drivers/iio/adc/qcom-pm8xxx-xoadc.c @@ -910,16 +910,15 @@ static int pm8xxx_xoadc_probe(struct platform_device *pdev) map = dev_get_regmap(dev->parent, NULL); if (!map) { dev_err(dev, "parent regmap unavailable.\n"); - return -ENXIO; + return -ENODEV; } adc->map = map; /* Bring up regulator */ adc->vref = devm_regulator_get(dev, "xoadc-ref"); - if (IS_ERR(adc->vref)) { - dev_err(dev, "failed to get XOADC VREF regulator\n"); - return PTR_ERR(adc->vref); - } + if (IS_ERR(adc->vref)) + return dev_err_probe(dev, PTR_ERR(adc->vref), + "failed to get XOADC VREF regulator\n"); ret = regulator_enable(adc->vref); if (ret) { dev_err(dev, "failed to enable XOADC VREF regulator\n"); diff --git a/drivers/iio/adc/rn5t618-adc.c b/drivers/iio/adc/rn5t618-adc.c index c56fccb2c8e1..7d891b4ea461 100644 --- a/drivers/iio/adc/rn5t618-adc.c +++ b/drivers/iio/adc/rn5t618-adc.c @@ -197,13 +197,6 @@ static struct iio_map rn5t618_maps[] = { { /* sentinel */ } }; -static void unregister_map(void *data) -{ - struct iio_dev *iio_dev = (struct iio_dev *) data; - - iio_map_array_unregister(iio_dev); -} - static int rn5t618_adc_probe(struct platform_device *pdev) { int ret; @@ -254,11 +247,7 @@ static int rn5t618_adc_probe(struct platform_device *pdev) return ret; } - ret = iio_map_array_register(iio_dev, rn5t618_maps); - if (ret < 0) - return ret; - - ret = devm_add_action_or_reset(adc->dev, unregister_map, iio_dev); + ret = devm_iio_map_array_register(adc->dev, iio_dev, rn5t618_maps); if (ret < 0) return ret; diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c index a237fe469a30..14b8df4ca9c8 100644 --- a/drivers/iio/adc/rockchip_saradc.c +++ b/drivers/iio/adc/rockchip_saradc.c @@ -319,7 +319,6 @@ static int rockchip_saradc_probe(struct platform_device *pdev) struct rockchip_saradc *info = NULL; struct device_node *np = pdev->dev.of_node; struct iio_dev *indio_dev = NULL; - struct resource *mem; const struct of_device_id *match; int ret; int irq; @@ -348,8 +347,7 @@ static int rockchip_saradc_probe(struct platform_device *pdev) return -EINVAL; } - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - info->regs = devm_ioremap_resource(&pdev->dev, mem); + info->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(info->regs)) return PTR_ERR(info->regs); @@ -362,7 +360,8 @@ static int rockchip_saradc_probe(struct platform_device *pdev) if (IS_ERR(info->reset)) { ret = PTR_ERR(info->reset); if (ret != -ENOENT) - return ret; + return dev_err_probe(&pdev->dev, ret, + "failed to get saradc-apb\n"); dev_dbg(&pdev->dev, "no reset control found\n"); info->reset = NULL; @@ -372,7 +371,7 @@ static int rockchip_saradc_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) - return irq; + return dev_err_probe(&pdev->dev, irq, "failed to get irq\n"); ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr, 0, dev_name(&pdev->dev), info); @@ -382,23 +381,19 @@ static int rockchip_saradc_probe(struct platform_device *pdev) } info->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); - if (IS_ERR(info->pclk)) { - dev_err(&pdev->dev, "failed to get pclk\n"); - return PTR_ERR(info->pclk); - } + if (IS_ERR(info->pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk), + "failed to get pclk\n"); info->clk = devm_clk_get(&pdev->dev, "saradc"); - if (IS_ERR(info->clk)) { - dev_err(&pdev->dev, "failed to get adc clock\n"); - return PTR_ERR(info->clk); - } + if (IS_ERR(info->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), + "failed to get adc clock\n"); info->vref = devm_regulator_get(&pdev->dev, "vref"); - if (IS_ERR(info->vref)) { - dev_err(&pdev->dev, "failed to get regulator, %ld\n", - PTR_ERR(info->vref)); - return PTR_ERR(info->vref); - } + if (IS_ERR(info->vref)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->vref), + "failed to get regulator\n"); if (info->reset) rockchip_saradc_reset_controller(info->reset); diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c index 9996d5eef289..32fbf57c362f 100644 --- a/drivers/iio/adc/rzg2l_adc.c +++ b/drivers/iio/adc/rzg2l_adc.c @@ -401,7 +401,7 @@ static int rzg2l_adc_hw_init(struct rzg2l_adc *adc) exit_hw_init: clk_disable_unprepare(adc->pclk); - return 0; + return ret; } static void rzg2l_adc_pm_runtime_disable(void *data) @@ -570,8 +570,10 @@ static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev) return ret; ret = clk_prepare_enable(adc->adclk); - if (ret) + if (ret) { + clk_disable_unprepare(adc->pclk); return ret; + } rzg2l_adc_pwr(adc, true); diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c index c088cb990193..b6e18eb101f7 100644 --- a/drivers/iio/adc/stm32-adc-core.c +++ b/drivers/iio/adc/stm32-adc-core.c @@ -659,6 +659,7 @@ static int stm32_adc_probe(struct platform_device *pdev) priv->cfg = (const struct stm32_adc_priv_cfg *) of_match_device(dev->driver->of_match_table, dev)->data; + spin_lock_init(&priv->common.lock); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); priv->common.base = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/iio/adc/stm32-adc-core.h b/drivers/iio/adc/stm32-adc-core.h index 2322809bfd2f..faedf7a49555 100644 --- a/drivers/iio/adc/stm32-adc-core.h +++ b/drivers/iio/adc/stm32-adc-core.h @@ -102,6 +102,9 @@ #define STM32H7_ADC_CALFACT 0xC4 #define STM32H7_ADC_CALFACT2 0xC8 +/* STM32MP1 - ADC2 instance option register */ +#define STM32MP1_ADC2_OR 0xD0 + /* STM32H7 - common registers for all ADC instances */ #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) @@ -168,23 +171,30 @@ enum stm32h7_adc_dmngt { #define STM32H7_EOC_MST BIT(2) /* STM32H7_ADC_CCR - bit fields */ +#define STM32H7_VBATEN BIT(24) +#define STM32H7_VREFEN BIT(22) #define STM32H7_PRESC_SHIFT 18 #define STM32H7_PRESC_MASK GENMASK(21, 18) #define STM32H7_CKMODE_SHIFT 16 #define STM32H7_CKMODE_MASK GENMASK(17, 16) +/* STM32MP1_ADC2_OR - bit fields */ +#define STM32MP1_VDDCOREEN BIT(0) + /** * struct stm32_adc_common - stm32 ADC driver common data (for all instances) * @base: control registers base cpu addr * @phys_base: control registers base physical addr * @rate: clock rate used for analog circuitry * @vref_mv: vref voltage (mv) + * @lock: spinlock */ struct stm32_adc_common { void __iomem *base; phys_addr_t phys_base; unsigned long rate; int vref_mv; + spinlock_t lock; /* lock for common register */ }; #endif diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c index 5088de835bb1..6245434f8377 100644 --- a/drivers/iio/adc/stm32-adc.c +++ b/drivers/iio/adc/stm32-adc.c @@ -21,6 +21,7 @@ #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> +#include <linux/nvmem-consumer.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/of.h> @@ -35,12 +36,13 @@ #define STM32H7_BOOST_CLKRATE 20000000UL #define STM32_ADC_CH_MAX 20 /* max number of channels */ -#define STM32_ADC_CH_SZ 10 /* max channel name size */ +#define STM32_ADC_CH_SZ 16 /* max channel name size */ #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */ #define STM32_ADC_TIMEOUT_US 100000 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) #define STM32_ADC_HW_STOP_DELAY_MS 100 +#define STM32_ADC_VREFINT_VOLTAGE 3300 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE @@ -77,6 +79,30 @@ enum stm32_adc_extsel { STM32_EXT20, }; +enum stm32_adc_int_ch { + STM32_ADC_INT_CH_NONE = -1, + STM32_ADC_INT_CH_VDDCORE, + STM32_ADC_INT_CH_VREFINT, + STM32_ADC_INT_CH_VBAT, + STM32_ADC_INT_CH_NB, +}; + +/** + * struct stm32_adc_ic - ADC internal channels + * @name: name of the internal channel + * @idx: internal channel enum index + */ +struct stm32_adc_ic { + const char *name; + u32 idx; +}; + +static const struct stm32_adc_ic stm32_adc_ic[STM32_ADC_INT_CH_NB] = { + { "vddcore", STM32_ADC_INT_CH_VDDCORE }, + { "vrefint", STM32_ADC_INT_CH_VREFINT }, + { "vbat", STM32_ADC_INT_CH_VBAT }, +}; + /** * struct stm32_adc_trig_info - ADC trigger info * @name: name of the trigger, corresponding to its source @@ -114,6 +140,16 @@ struct stm32_adc_regs { }; /** + * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data + * @vrefint_cal: vrefint calibration value from nvmem + * @vrefint_data: vrefint actual value + */ +struct stm32_adc_vrefint { + u32 vrefint_cal; + u32 vrefint_data; +}; + +/** * struct stm32_adc_regspec - stm32 registers definition * @dr: data register offset * @ier_eoc: interrupt enable register & eocie bitfield @@ -126,6 +162,9 @@ struct stm32_adc_regs { * @res: resolution selection register & bitfield * @smpr: smpr1 & smpr2 registers offset array * @smp_bits: smpr1 & smpr2 index and bitfields + * @or_vdd: option register & vddcore bitfield + * @ccr_vbat: common register & vbat bitfield + * @ccr_vref: common register & vrefint bitfield */ struct stm32_adc_regspec { const u32 dr; @@ -139,6 +178,9 @@ struct stm32_adc_regspec { const struct stm32_adc_regs res; const u32 smpr[2]; const struct stm32_adc_regs *smp_bits; + const struct stm32_adc_regs or_vdd; + const struct stm32_adc_regs ccr_vbat; + const struct stm32_adc_regs ccr_vref; }; struct stm32_adc; @@ -156,6 +198,7 @@ struct stm32_adc; * @unprepare: optional unprepare routine (disable, power-down) * @irq_clear: routine to clear irqs * @smp_cycles: programmable sampling time (ADC clock cycles) + * @ts_vrefint_ns: vrefint minimum sampling time in ns */ struct stm32_adc_cfg { const struct stm32_adc_regspec *regs; @@ -169,6 +212,7 @@ struct stm32_adc_cfg { void (*unprepare)(struct iio_dev *); void (*irq_clear)(struct iio_dev *indio_dev, u32 msk); const unsigned int *smp_cycles; + const unsigned int ts_vrefint_ns; }; /** @@ -193,7 +237,10 @@ struct stm32_adc_cfg { * @pcsel: bitmask to preselect channels on some devices * @smpr_val: sampling time settings (e.g. smpr1 / smpr2) * @cal: optional calibration data on some devices + * @vrefint: internal reference voltage data * @chan_name: channel name array + * @num_diff: number of differential channels + * @int_ch: internal channel indexes array */ struct stm32_adc { struct stm32_adc_common *common; @@ -216,7 +263,10 @@ struct stm32_adc { u32 pcsel; u32 smpr_val[2]; struct stm32_adc_calib cal; + struct stm32_adc_vrefint vrefint; char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ]; + u32 num_diff; + int int_ch[STM32_ADC_INT_CH_NB]; }; struct stm32_adc_diff_channel { @@ -449,6 +499,24 @@ static const struct stm32_adc_regspec stm32h7_adc_regspec = { .smp_bits = stm32h7_smp_bits, }; +static const struct stm32_adc_regspec stm32mp1_adc_regspec = { + .dr = STM32H7_ADC_DR, + .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, + .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, + .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, + .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, + .sqr = stm32h7_sq, + .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, + .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, + STM32H7_EXTSEL_SHIFT }, + .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, + .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, + .smp_bits = stm32h7_smp_bits, + .or_vdd = { STM32MP1_ADC2_OR, STM32MP1_VDDCOREEN }, + .ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN }, + .ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN }, +}; + /* * STM32 ADC registers access routines * @adc: stm32 adc instance @@ -487,6 +555,14 @@ static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) spin_unlock_irqrestore(&adc->lock, flags); } +static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) +{ + spin_lock(&adc->common->lock); + writel_relaxed(readl_relaxed(adc->common->base + reg) | bits, + adc->common->base + reg); + spin_unlock(&adc->common->lock); +} + static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) { unsigned long flags; @@ -496,6 +572,14 @@ static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) spin_unlock_irqrestore(&adc->lock, flags); } +static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) +{ + spin_lock(&adc->common->lock); + writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits, + adc->common->base + reg); + spin_unlock(&adc->common->lock); +} + /** * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt * @adc: stm32 adc instance @@ -577,6 +661,60 @@ err_clk_dis: return ret; } +static void stm32_adc_int_ch_enable(struct iio_dev *indio_dev) +{ + struct stm32_adc *adc = iio_priv(indio_dev); + u32 i; + + for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { + if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) + continue; + + switch (i) { + case STM32_ADC_INT_CH_VDDCORE: + dev_dbg(&indio_dev->dev, "Enable VDDCore\n"); + stm32_adc_set_bits(adc, adc->cfg->regs->or_vdd.reg, + adc->cfg->regs->or_vdd.mask); + break; + case STM32_ADC_INT_CH_VREFINT: + dev_dbg(&indio_dev->dev, "Enable VREFInt\n"); + stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg, + adc->cfg->regs->ccr_vref.mask); + break; + case STM32_ADC_INT_CH_VBAT: + dev_dbg(&indio_dev->dev, "Enable VBAT\n"); + stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, + adc->cfg->regs->ccr_vbat.mask); + break; + } + } +} + +static void stm32_adc_int_ch_disable(struct stm32_adc *adc) +{ + u32 i; + + for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { + if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) + continue; + + switch (i) { + case STM32_ADC_INT_CH_VDDCORE: + stm32_adc_clr_bits(adc, adc->cfg->regs->or_vdd.reg, + adc->cfg->regs->or_vdd.mask); + break; + case STM32_ADC_INT_CH_VREFINT: + stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, + adc->cfg->regs->ccr_vref.mask); + break; + case STM32_ADC_INT_CH_VBAT: + stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, + adc->cfg->regs->ccr_vbat.mask); + break; + } + } +} + /** * stm32f4_adc_start_conv() - Start conversions for regular channels. * @indio_dev: IIO device instance @@ -945,11 +1083,13 @@ static int stm32h7_adc_prepare(struct iio_dev *indio_dev) goto pwr_dwn; calib = ret; + stm32_adc_int_ch_enable(indio_dev); + stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); ret = stm32h7_adc_enable(indio_dev); if (ret) - goto pwr_dwn; + goto ch_disable; /* Either restore or read calibration result for future reference */ if (calib) @@ -965,6 +1105,8 @@ static int stm32h7_adc_prepare(struct iio_dev *indio_dev) disable: stm32h7_adc_disable(indio_dev); +ch_disable: + stm32_adc_int_ch_disable(adc); pwr_dwn: stm32h7_adc_enter_pwr_down(adc); @@ -976,6 +1118,7 @@ static void stm32h7_adc_unprepare(struct iio_dev *indio_dev) struct stm32_adc *adc = iio_priv(indio_dev); stm32h7_adc_disable(indio_dev); + stm32_adc_int_ch_disable(adc); stm32h7_adc_enter_pwr_down(adc); } @@ -1212,6 +1355,7 @@ static int stm32_adc_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_RAW: + case IIO_CHAN_INFO_PROCESSED: ret = iio_device_claim_direct_mode(indio_dev); if (ret) return ret; @@ -1219,6 +1363,10 @@ static int stm32_adc_read_raw(struct iio_dev *indio_dev, ret = stm32_adc_single_conv(indio_dev, chan, val); else ret = -EINVAL; + + if (mask == IIO_CHAN_INFO_PROCESSED && adc->vrefint.vrefint_cal) + *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val; + iio_device_release_direct_mode(indio_dev); return ret; @@ -1657,6 +1805,13 @@ static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) u32 period_ns, shift = smpr->shift, mask = smpr->mask; unsigned int smp, r = smpr->reg; + /* + * For vrefint channel, ensure that the sampling time cannot + * be lower than the one specified in the datasheet + */ + if (channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) + smp_ns = max(smp_ns, adc->cfg->ts_vrefint_ns); + /* Determine sampling time (ADC clock cycles) */ period_ns = NSEC_PER_SEC / adc->common->rate; for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++) @@ -1688,7 +1843,10 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, chan->datasheet_name = name; chan->scan_index = scan_index; chan->indexed = 1; - chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); + if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) + chan->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); + else + chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET); chan->scan_type.sign = 'u'; @@ -1706,17 +1864,11 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, } } -static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, bool timestamping) +static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) { struct device_node *node = indio_dev->dev.of_node; - struct stm32_adc *adc = iio_priv(indio_dev); const struct stm32_adc_info *adc_info = adc->cfg->adc_info; - struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; - struct property *prop; - const __be32 *cur; - struct iio_chan_spec *channels; - int scan_index = 0, num_channels = 0, num_diff = 0, ret, i; - u32 val, smp = 0; + int num_channels = 0, ret; ret = of_property_count_u32_elems(node, "st,adc-channels"); if (ret > adc_info->max_channels) { @@ -1727,24 +1879,13 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, bool timestamping) } ret = of_property_count_elems_of_size(node, "st,adc-diff-channels", - sizeof(*diff)); + sizeof(struct stm32_adc_diff_channel)); if (ret > adc_info->max_channels) { dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); return -EINVAL; } else if (ret > 0) { - int size = ret * sizeof(*diff) / sizeof(u32); - - num_diff = ret; + adc->num_diff = ret; num_channels += ret; - ret = of_property_read_u32_array(node, "st,adc-diff-channels", - (u32 *)diff, size); - if (ret) - return ret; - } - - if (!num_channels) { - dev_err(&indio_dev->dev, "No channels configured\n"); - return -ENODATA; } /* Optional sample time is provided either for each, or all channels */ @@ -1754,13 +1895,45 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, bool timestamping) return -EINVAL; } - if (timestamping) - num_channels++; + return num_channels; +} - channels = devm_kcalloc(&indio_dev->dev, num_channels, - sizeof(struct iio_chan_spec), GFP_KERNEL); - if (!channels) - return -ENOMEM; +static int stm32_adc_legacy_chan_init(struct iio_dev *indio_dev, + struct stm32_adc *adc, + struct iio_chan_spec *channels) +{ + struct device_node *node = indio_dev->dev.of_node; + const struct stm32_adc_info *adc_info = adc->cfg->adc_info; + struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; + u32 num_diff = adc->num_diff; + int size = num_diff * sizeof(*diff) / sizeof(u32); + int scan_index = 0, val, ret, i; + struct property *prop; + const __be32 *cur; + u32 smp = 0; + + if (num_diff) { + ret = of_property_read_u32_array(node, "st,adc-diff-channels", + (u32 *)diff, size); + if (ret) { + dev_err(&indio_dev->dev, "Failed to get diff channels %d\n", ret); + return ret; + } + + for (i = 0; i < num_diff; i++) { + if (diff[i].vinp >= adc_info->max_channels || + diff[i].vinn >= adc_info->max_channels) { + dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", + diff[i].vinp, diff[i].vinn); + return -EINVAL; + } + + stm32_adc_chan_init_one(indio_dev, &channels[scan_index], + diff[i].vinp, diff[i].vinn, + scan_index, true); + scan_index++; + } + } of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { if (val >= adc_info->max_channels) { @@ -1771,8 +1944,7 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, bool timestamping) /* Channel can't be configured both as single-ended & diff */ for (i = 0; i < num_diff; i++) { if (val == diff[i].vinp) { - dev_err(&indio_dev->dev, - "channel %d miss-configured\n", val); + dev_err(&indio_dev->dev, "channel %d misconfigured\n", val); return -EINVAL; } } @@ -1781,19 +1953,6 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, bool timestamping) scan_index++; } - for (i = 0; i < num_diff; i++) { - if (diff[i].vinp >= adc_info->max_channels || - diff[i].vinn >= adc_info->max_channels) { - dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", - diff[i].vinp, diff[i].vinn); - return -EINVAL; - } - stm32_adc_chan_init_one(indio_dev, &channels[scan_index], - diff[i].vinp, diff[i].vinn, scan_index, - true); - scan_index++; - } - for (i = 0; i < scan_index; i++) { /* * Using of_property_read_u32_index(), smp value will only be @@ -1801,12 +1960,178 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, bool timestamping) * get either no value, 1 shared value for all indexes, or one * value per channel. */ - of_property_read_u32_index(node, "st,min-sample-time-nsecs", - i, &smp); + of_property_read_u32_index(node, "st,min-sample-time-nsecs", i, &smp); + /* Prepare sampling time settings */ stm32_adc_smpr_init(adc, channels[i].channel, smp); } + return scan_index; +} + +static int stm32_adc_populate_int_ch(struct iio_dev *indio_dev, const char *ch_name, + int chan) +{ + struct stm32_adc *adc = iio_priv(indio_dev); + u16 vrefint; + int i, ret; + + for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { + if (!strncmp(stm32_adc_ic[i].name, ch_name, STM32_ADC_CH_SZ)) { + adc->int_ch[i] = chan; + + if (stm32_adc_ic[i].idx != STM32_ADC_INT_CH_VREFINT) + continue; + + /* Get calibration data for vrefint channel */ + ret = nvmem_cell_read_u16(&indio_dev->dev, "vrefint", &vrefint); + if (ret && ret != -ENOENT) { + return dev_err_probe(&indio_dev->dev, ret, + "nvmem access error\n"); + } + if (ret == -ENOENT) + dev_dbg(&indio_dev->dev, "vrefint calibration not found\n"); + else + adc->vrefint.vrefint_cal = vrefint; + } + } + + return 0; +} + +static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev, + struct stm32_adc *adc, + struct iio_chan_spec *channels) +{ + struct device_node *node = indio_dev->dev.of_node; + const struct stm32_adc_info *adc_info = adc->cfg->adc_info; + struct device_node *child; + const char *name; + int val, scan_index = 0, ret; + bool differential; + u32 vin[2]; + + for_each_available_child_of_node(node, child) { + ret = of_property_read_u32(child, "reg", &val); + if (ret) { + dev_err(&indio_dev->dev, "Missing channel index %d\n", ret); + goto err; + } + + ret = of_property_read_string(child, "label", &name); + /* label is optional */ + if (!ret) { + if (strlen(name) >= STM32_ADC_CH_SZ) { + dev_err(&indio_dev->dev, "Label %s exceeds %d characters\n", + name, STM32_ADC_CH_SZ); + return -EINVAL; + } + strncpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); + ret = stm32_adc_populate_int_ch(indio_dev, name, val); + if (ret) + goto err; + } else if (ret != -EINVAL) { + dev_err(&indio_dev->dev, "Invalid label %d\n", ret); + goto err; + } + + if (val >= adc_info->max_channels) { + dev_err(&indio_dev->dev, "Invalid channel %d\n", val); + ret = -EINVAL; + goto err; + } + + differential = false; + ret = of_property_read_u32_array(child, "diff-channels", vin, 2); + /* diff-channels is optional */ + if (!ret) { + differential = true; + if (vin[0] != val || vin[1] >= adc_info->max_channels) { + dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", + vin[0], vin[1]); + goto err; + } + } else if (ret != -EINVAL) { + dev_err(&indio_dev->dev, "Invalid diff-channels property %d\n", ret); + goto err; + } + + stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, + vin[1], scan_index, differential); + + ret = of_property_read_u32(child, "st,min-sample-time-ns", &val); + /* st,min-sample-time-ns is optional */ + if (!ret) { + stm32_adc_smpr_init(adc, channels[scan_index].channel, val); + if (differential) + stm32_adc_smpr_init(adc, vin[1], val); + } else if (ret != -EINVAL) { + dev_err(&indio_dev->dev, "Invalid st,min-sample-time-ns property %d\n", + ret); + goto err; + } + + scan_index++; + } + + return scan_index; + +err: + of_node_put(child); + + return ret; +} + +static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, bool timestamping) +{ + struct device_node *node = indio_dev->dev.of_node; + struct stm32_adc *adc = iio_priv(indio_dev); + const struct stm32_adc_info *adc_info = adc->cfg->adc_info; + struct iio_chan_spec *channels; + int scan_index = 0, num_channels = 0, ret, i; + bool legacy = false; + + for (i = 0; i < STM32_ADC_INT_CH_NB; i++) + adc->int_ch[i] = STM32_ADC_INT_CH_NONE; + + num_channels = of_get_available_child_count(node); + /* If no channels have been found, fallback to channels legacy properties. */ + if (!num_channels) { + legacy = true; + + ret = stm32_adc_get_legacy_chan_count(indio_dev, adc); + if (!ret) { + dev_err(indio_dev->dev.parent, "No channel found\n"); + return -ENODATA; + } else if (ret < 0) { + return ret; + } + + num_channels = ret; + } + + if (num_channels > adc_info->max_channels) { + dev_err(&indio_dev->dev, "Channel number [%d] exceeds %d\n", + num_channels, adc_info->max_channels); + return -EINVAL; + } + + if (timestamping) + num_channels++; + + channels = devm_kcalloc(&indio_dev->dev, num_channels, + sizeof(struct iio_chan_spec), GFP_KERNEL); + if (!channels) + return -ENOMEM; + + if (legacy) + ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels); + else + ret = stm32_adc_generic_chan_init(indio_dev, adc, channels); + if (ret < 0) + return ret; + scan_index = ret; + if (timestamping) { struct iio_chan_spec *timestamp = &channels[scan_index]; @@ -2099,7 +2424,7 @@ static const struct stm32_adc_cfg stm32h7_adc_cfg = { }; static const struct stm32_adc_cfg stm32mp1_adc_cfg = { - .regs = &stm32h7_adc_regspec, + .regs = &stm32mp1_adc_regspec, .adc_info = &stm32h7_adc_info, .trigs = stm32h7_adc_trigs, .has_vregready = true, @@ -2109,6 +2434,7 @@ static const struct stm32_adc_cfg stm32mp1_adc_cfg = { .unprepare = stm32h7_adc_unprepare, .smp_cycles = stm32h7_adc_smp_cycles, .irq_clear = stm32h7_adc_irq_clear, + .ts_vrefint_ns = 4300, }; static const struct of_device_id stm32_adc_of_match[] = { diff --git a/drivers/iio/adc/ti-adc108s102.c b/drivers/iio/adc/ti-adc108s102.c index db902aef2abe..c8e48881c37f 100644 --- a/drivers/iio/adc/ti-adc108s102.c +++ b/drivers/iio/adc/ti-adc108s102.c @@ -75,9 +75,9 @@ struct adc108s102_state { * rx_buf: |XX|R0|R1|R2|R3|R4|R5|R6|R7|tt|tt|tt|tt| * * tx_buf: 8 channel read commands, plus 1 dummy command - * rx_buf: 1 dummy response, 8 channel responses, plus 64-bit timestamp + * rx_buf: 1 dummy response, 8 channel responses */ - __be16 rx_buf[13] ____cacheline_aligned; + __be16 rx_buf[9] ____cacheline_aligned; __be16 tx_buf[9] ____cacheline_aligned; }; @@ -149,9 +149,10 @@ static irqreturn_t adc108s102_trigger_handler(int irq, void *p) goto out_notify; /* Skip the dummy response in the first slot */ - iio_push_to_buffers_with_timestamp(indio_dev, - (u8 *)&st->rx_buf[1], - iio_get_time_ns(indio_dev)); + iio_push_to_buffers_with_ts_unaligned(indio_dev, + &st->rx_buf[1], + st->ring_xfer.len - sizeof(st->rx_buf[1]), + iio_get_time_ns(indio_dev)); out_notify: iio_trigger_notify_done(indio_dev->trig); diff --git a/drivers/iio/adc/ti-adc128s052.c b/drivers/iio/adc/ti-adc128s052.c index 3143f35a6509..8e7adec87755 100644 --- a/drivers/iio/adc/ti-adc128s052.c +++ b/drivers/iio/adc/ti-adc128s052.c @@ -132,6 +132,11 @@ static const struct iio_info adc128_info = { .read_raw = adc128_read_raw, }; +static void adc128_disable_regulator(void *reg) +{ + regulator_disable(reg); +} + static int adc128_probe(struct spi_device *spi) { struct iio_dev *indio_dev; @@ -151,8 +156,6 @@ static int adc128_probe(struct spi_device *spi) adc = iio_priv(indio_dev); adc->spi = spi; - spi_set_drvdata(spi, indio_dev); - indio_dev->name = spi_get_device_id(spi)->name; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &adc128_info; @@ -167,23 +170,14 @@ static int adc128_probe(struct spi_device *spi) ret = regulator_enable(adc->reg); if (ret < 0) return ret; + ret = devm_add_action_or_reset(&spi->dev, adc128_disable_regulator, + adc->reg); + if (ret) + return ret; mutex_init(&adc->lock); - ret = iio_device_register(indio_dev); - - return ret; -} - -static int adc128_remove(struct spi_device *spi) -{ - struct iio_dev *indio_dev = spi_get_drvdata(spi); - struct adc128 *adc = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - regulator_disable(adc->reg); - - return 0; + return devm_iio_device_register(&spi->dev, indio_dev); } static const struct of_device_id adc128_of_match[] = { @@ -225,7 +219,6 @@ static struct spi_driver adc128_driver = { .acpi_match_table = ACPI_PTR(adc128_acpi_match), }, .probe = adc128_probe, - .remove = adc128_remove, .id_table = adc128_id, }; module_spi_driver(adc128_driver); diff --git a/drivers/iio/adc/ti-ads7950.c b/drivers/iio/adc/ti-ads7950.c index a2b83f0bd526..a7efa3eada2c 100644 --- a/drivers/iio/adc/ti-ads7950.c +++ b/drivers/iio/adc/ti-ads7950.c @@ -600,8 +600,8 @@ static int ti_ads7950_probe(struct spi_device *spi) st->reg = devm_regulator_get(&spi->dev, "vref"); if (IS_ERR(st->reg)) { - dev_err(&spi->dev, "Failed to get regulator \"vref\"\n"); - ret = PTR_ERR(st->reg); + ret = dev_err_probe(&spi->dev, PTR_ERR(st->reg), + "Failed to get regulator \"vref\"\n"); goto error_destroy_mutex; } diff --git a/drivers/iio/adc/ti-ads8344.c b/drivers/iio/adc/ti-ads8344.c index a345a30d74fa..c96d2a9ba924 100644 --- a/drivers/iio/adc/ti-ads8344.c +++ b/drivers/iio/adc/ti-ads8344.c @@ -133,6 +133,11 @@ static const struct iio_info ads8344_info = { .read_raw = ads8344_read_raw, }; +static void ads8344_reg_disable(void *data) +{ + regulator_disable(data); +} + static int ads8344_probe(struct spi_device *spi) { struct iio_dev *indio_dev; @@ -161,26 +166,11 @@ static int ads8344_probe(struct spi_device *spi) if (ret) return ret; - spi_set_drvdata(spi, indio_dev); - - ret = iio_device_register(indio_dev); - if (ret) { - regulator_disable(adc->reg); + ret = devm_add_action_or_reset(&spi->dev, ads8344_reg_disable, adc->reg); + if (ret) return ret; - } - - return 0; -} - -static int ads8344_remove(struct spi_device *spi) -{ - struct iio_dev *indio_dev = spi_get_drvdata(spi); - struct ads8344 *adc = iio_priv(indio_dev); - - iio_device_unregister(indio_dev); - regulator_disable(adc->reg); - return 0; + return devm_iio_device_register(&spi->dev, indio_dev); } static const struct of_device_id ads8344_of_match[] = { @@ -195,7 +185,6 @@ static struct spi_driver ads8344_driver = { .of_match_table = ads8344_of_match, }, .probe = ads8344_probe, - .remove = ads8344_remove, }; module_spi_driver(ads8344_driver); diff --git a/drivers/iio/adc/ti-tsc2046.c b/drivers/iio/adc/ti-tsc2046.c index 170950d5dd49..d84ae6b008c1 100644 --- a/drivers/iio/adc/ti-tsc2046.c +++ b/drivers/iio/adc/ti-tsc2046.c @@ -398,7 +398,7 @@ static int tsc2046_adc_update_scan_mode(struct iio_dev *indio_dev, priv->xfer.len = size; priv->time_per_scan_us = size * 8 * priv->time_per_bit_ns / NSEC_PER_USEC; - if (priv->scan_interval_us > priv->time_per_scan_us) + if (priv->scan_interval_us < priv->time_per_scan_us) dev_warn(&priv->spi->dev, "The scan interval (%d) is less then calculated scan time (%d)\n", priv->scan_interval_us, priv->time_per_scan_us); diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c index 855cc2d64ac8..dbdc1ef48566 100644 --- a/drivers/iio/adc/ti_am335x_adc.c +++ b/drivers/iio/adc/ti_am335x_adc.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI ADC MFD driver * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> @@ -25,6 +17,7 @@ #include <linux/of_device.h> #include <linux/iio/machine.h> #include <linux/iio/driver.h> +#include <linux/iopoll.h> #include <linux/mfd/ti_am335x_tscadc.h> #include <linux/iio/buffer.h> @@ -65,7 +58,7 @@ static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg) } static void tiadc_writel(struct tiadc_device *adc, unsigned int reg, - unsigned int val) + unsigned int val) { writel(val, adc->mfd_tscadc->tscadc_base + reg); } @@ -80,7 +73,7 @@ static u32 get_adc_step_mask(struct tiadc_device *adc_dev) } static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev, - struct iio_chan_spec const *chan) + struct iio_chan_spec const *chan) { int i; @@ -102,10 +95,18 @@ static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan) return 1 << adc_dev->channel_step[chan]; } +static int tiadc_wait_idle(struct tiadc_device *adc_dev) +{ + u32 val; + + return readl_poll_timeout(adc_dev->mfd_tscadc->tscadc_base + REG_ADCFSM, + val, !(val & SEQ_STATUS), 10, + IDLE_TIMEOUT_MS * 1000 * adc_dev->channels); +} + static void tiadc_step_config(struct iio_dev *indio_dev) { struct tiadc_device *adc_dev = iio_priv(indio_dev); - struct device *dev = adc_dev->mfd_tscadc->dev; unsigned int stepconfig; int i, steps = 0; @@ -118,23 +119,14 @@ static void tiadc_step_config(struct iio_dev *indio_dev) * Channel would represent which analog input * needs to be given to ADC to digitalize data. */ - - for (i = 0; i < adc_dev->channels; i++) { int chan; chan = adc_dev->channel_line[i]; - if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) { - dev_warn(dev, "chan %d step_avg truncating to %d\n", - chan, STEPCONFIG_AVG_16); - adc_dev->step_avg[i] = STEPCONFIG_AVG_16; - } - if (adc_dev->step_avg[i]) - stepconfig = - STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | - STEPCONFIG_FIFO1; + stepconfig = STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | + STEPCONFIG_FIFO1; else stepconfig = STEPCONFIG_FIFO1; @@ -142,26 +134,13 @@ static void tiadc_step_config(struct iio_dev *indio_dev) stepconfig |= STEPCONFIG_MODE_SWCNT; tiadc_writel(adc_dev, REG_STEPCONFIG(steps), - stepconfig | STEPCONFIG_INP(chan) | - STEPCONFIG_INM_ADCREFM | - STEPCONFIG_RFP_VREFP | - STEPCONFIG_RFM_VREFN); - - if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) { - dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n", - chan); - adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK; - } - - if (adc_dev->sample_delay[i] > 0xFF) { - dev_warn(dev, "chan %d sample delay truncating to 0xFF\n", - chan); - adc_dev->sample_delay[i] = 0xFF; - } + stepconfig | STEPCONFIG_INP(chan) | + STEPCONFIG_INM_ADCREFM | STEPCONFIG_RFP_VREFP | + STEPCONFIG_RFM_VREFN); tiadc_writel(adc_dev, REG_STEPDELAY(steps), - STEPDELAY_OPEN(adc_dev->open_delay[i]) | - STEPDELAY_SAMPLE(adc_dev->sample_delay[i])); + STEPDELAY_OPEN(adc_dev->open_delay[i]) | + STEPDELAY_SAMPLE(adc_dev->sample_delay[i])); adc_dev->channel_step[i] = steps; steps++; @@ -184,12 +163,14 @@ static irqreturn_t tiadc_irq_h(int irq, void *private) if (status & IRQENB_FIFO1OVRRUN) { /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */ config = tiadc_readl(adc_dev, REG_CTRL); - config &= ~(CNTRLREG_TSCSSENB); + config &= ~(CNTRLREG_SSENB); tiadc_writel(adc_dev, REG_CTRL, config); - tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN - | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES); + tiadc_writel(adc_dev, REG_IRQSTATUS, + IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW | + IRQENB_FIFO1THRES); - /* wait for idle state. + /* + * Wait for the idle state. * ADC needs to finish the current conversion * before disabling the module */ @@ -197,7 +178,7 @@ static irqreturn_t tiadc_irq_h(int irq, void *private) adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM); } while (adc_fsm != 0x10 && count++ < 100); - tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB)); + tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_SSENB)); return IRQ_HANDLED; } else if (status & IRQENB_FIFO1THRES) { /* Disable irq and wake worker thread */ @@ -217,11 +198,11 @@ static irqreturn_t tiadc_worker_h(int irq, void *private) fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); for (k = 0; k < fifo1count; k = k + i) { - for (i = 0; i < (indio_dev->scan_bytes)/2; i++) { + for (i = 0; i < indio_dev->scan_bytes / 2; i++) { read = tiadc_readl(adc_dev, REG_FIFO1); data[i] = read & FIFOREAD_DATA_MASK; } - iio_push_to_buffers(indio_dev, (u8 *) data); + iio_push_to_buffers(indio_dev, (u8 *)data); } tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES); @@ -254,6 +235,7 @@ static int tiadc_start_dma(struct iio_dev *indio_dev) struct dma_async_tx_descriptor *desc; dma->current_period = 0; /* We start to fill period 0 */ + /* * Make the fifo thresh as the multiple of total number of * channels enabled, so make sure that cyclic DMA period @@ -263,9 +245,10 @@ static int tiadc_start_dma(struct iio_dev *indio_dev) */ dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1, adc_dev->total_ch_enabled) - 1; + /* Make sure that period length is multiple of fifo thresh level */ dma->period_size = rounddown(DMA_BUFFER_SIZE / 2, - (dma->fifo_thresh + 1) * sizeof(u16)); + (dma->fifo_thresh + 1) * sizeof(u16)); dma->conf.src_maxburst = dma->fifo_thresh + 1; dmaengine_slave_config(dma->chan, &dma->conf); @@ -295,10 +278,15 @@ static int tiadc_buffer_preenable(struct iio_dev *indio_dev) { struct tiadc_device *adc_dev = iio_priv(indio_dev); int i, fifo1count; + int ret; + + ret = tiadc_wait_idle(adc_dev); + if (ret) + return ret; - tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | - IRQENB_FIFO1OVRRUN | - IRQENB_FIFO1UNDRFLW)); + tiadc_writel(adc_dev, REG_IRQCLR, + IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN | + IRQENB_FIFO1UNDRFLW); /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */ fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); @@ -328,8 +316,9 @@ static int tiadc_buffer_postenable(struct iio_dev *indio_dev) am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb); - tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES - | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW); + tiadc_writel(adc_dev, REG_IRQSTATUS, + IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN | + IRQENB_FIFO1UNDRFLW); irq_enable = IRQENB_FIFO1OVRRUN; if (!dma->chan) @@ -345,8 +334,9 @@ static int tiadc_buffer_predisable(struct iio_dev *indio_dev) struct tiadc_dma *dma = &adc_dev->dma; int fifo1count, i; - tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | - IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW)); + tiadc_writel(adc_dev, REG_IRQCLR, + IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN | + IRQENB_FIFO1UNDRFLW); am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps); adc_dev->buffer_en_ch_steps = 0; adc_dev->total_ch_enabled = 0; @@ -378,12 +368,11 @@ static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = { }; static int tiadc_iio_buffered_hardware_setup(struct device *dev, - struct iio_dev *indio_dev, - irqreturn_t (*pollfunc_bh)(int irq, void *p), - irqreturn_t (*pollfunc_th)(int irq, void *p), - int irq, - unsigned long flags, - const struct iio_buffer_setup_ops *setup_ops) + struct iio_dev *indio_dev, + irqreturn_t (*pollfunc_bh)(int irq, void *p), + irqreturn_t (*pollfunc_th)(int irq, void *p), + int irq, unsigned long flags, + const struct iio_buffer_setup_ops *setup_ops) { int ret; @@ -394,7 +383,7 @@ static int tiadc_iio_buffered_hardware_setup(struct device *dev, return ret; return devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh, - flags, indio_dev->name, indio_dev); + flags, indio_dev->name, indio_dev); } static const char * const chan_name_ain[] = { @@ -419,16 +408,16 @@ static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev, indio_dev->num_channels = channels; chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array), GFP_KERNEL); - if (chan_array == NULL) + if (!chan_array) return -ENOMEM; chan = chan_array; for (i = 0; i < channels; i++, chan++) { - chan->type = IIO_VOLTAGE; chan->indexed = 1; chan->channel = adc_dev->channel_line[i]; chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); + chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); chan->datasheet_name = chan_name_ain[chan->channel]; chan->scan_index = i; chan->scan_type.sign = 'u'; @@ -442,16 +431,33 @@ static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev, } static int tiadc_read_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int *val, int *val2, long mask) + struct iio_chan_spec const *chan, int *val, int *val2, + long mask) { struct tiadc_device *adc_dev = iio_priv(indio_dev); - int ret = IIO_VAL_INT; int i, map_val; unsigned int fifo1count, read, stepid; bool found = false; u32 step_en; unsigned long timeout; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + break; + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_VOLTAGE: + *val = 1800; + *val2 = chan->scan_type.realbits; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } if (iio_buffer_enabled(indio_dev)) return -EBUSY; @@ -461,15 +467,19 @@ static int tiadc_read_raw(struct iio_dev *indio_dev, return -EINVAL; mutex_lock(&adc_dev->fifo1_lock); + + ret = tiadc_wait_idle(adc_dev); + if (ret) + goto err_unlock; + fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); while (fifo1count--) tiadc_readl(adc_dev, REG_FIFO1); am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en); - timeout = jiffies + msecs_to_jiffies - (IDLE_TIMEOUT * adc_dev->channels); /* Wait for Fifo threshold interrupt */ + timeout = jiffies + msecs_to_jiffies(IDLE_TIMEOUT_MS * adc_dev->channels); while (1) { fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); if (fifo1count) @@ -481,6 +491,7 @@ static int tiadc_read_raw(struct iio_dev *indio_dev, goto err_unlock; } } + map_val = adc_dev->channel_step[chan->scan_index]; /* @@ -498,17 +509,18 @@ static int tiadc_read_raw(struct iio_dev *indio_dev, if (stepid == map_val) { read = read & FIFOREAD_DATA_MASK; found = true; - *val = (u16) read; + *val = (u16)read; } } + am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); if (!found) - ret = -EBUSY; + ret = -EBUSY; err_unlock: mutex_unlock(&adc_dev->fifo1_lock); - return ret; + return ret ? ret : IIO_VAL_INT; } static const struct iio_info tiadc_info = { @@ -545,6 +557,7 @@ static int tiadc_request_dma(struct platform_device *pdev, goto err; return 0; + err: dma_release_channel(dma->chan); return -ENOMEM; @@ -558,6 +571,7 @@ static int tiadc_parse_dt(struct platform_device *pdev, const __be32 *cur; int channels = 0; u32 val; + int i; of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { adc_dev->channel_line[channels] = val; @@ -570,6 +584,8 @@ static int tiadc_parse_dt(struct platform_device *pdev, channels++; } + adc_dev->channels = channels; + of_property_read_u32_array(node, "ti,chan-step-avg", adc_dev->step_avg, channels); of_property_read_u32_array(node, "ti,chan-step-opendelay", @@ -577,7 +593,33 @@ static int tiadc_parse_dt(struct platform_device *pdev, of_property_read_u32_array(node, "ti,chan-step-sampledelay", adc_dev->sample_delay, channels); - adc_dev->channels = channels; + for (i = 0; i < adc_dev->channels; i++) { + int chan; + + chan = adc_dev->channel_line[i]; + + if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) { + dev_warn(&pdev->dev, + "chan %d: wrong step avg, truncated to %ld\n", + chan, STEPCONFIG_AVG_16); + adc_dev->step_avg[i] = STEPCONFIG_AVG_16; + } + + if (adc_dev->open_delay[i] > STEPCONFIG_MAX_OPENDLY) { + dev_warn(&pdev->dev, + "chan %d: wrong open delay, truncated to 0x%lX\n", + chan, STEPCONFIG_MAX_OPENDLY); + adc_dev->open_delay[i] = STEPCONFIG_MAX_OPENDLY; + } + + if (adc_dev->sample_delay[i] > STEPCONFIG_MAX_SAMPLE) { + dev_warn(&pdev->dev, + "chan %d: wrong sample delay, truncated to 0x%lX\n", + chan, STEPCONFIG_MAX_SAMPLE); + adc_dev->sample_delay[i] = STEPCONFIG_MAX_SAMPLE; + } + } + return 0; } @@ -594,7 +636,7 @@ static int tiadc_probe(struct platform_device *pdev) } indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev)); - if (indio_dev == NULL) { + if (!indio_dev) { dev_err(&pdev->dev, "failed to allocate iio device\n"); return -ENOMEM; } @@ -616,18 +658,17 @@ static int tiadc_probe(struct platform_device *pdev) return err; err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev, - &tiadc_worker_h, - &tiadc_irq_h, - adc_dev->mfd_tscadc->irq, - IRQF_SHARED, - &tiadc_buffer_setup_ops); - + &tiadc_worker_h, + &tiadc_irq_h, + adc_dev->mfd_tscadc->irq, + IRQF_SHARED, + &tiadc_buffer_setup_ops); if (err) - goto err_free_channels; + return err; err = iio_device_register(indio_dev); if (err) - goto err_buffer_unregister; + return err; platform_set_drvdata(pdev, indio_dev); @@ -639,8 +680,7 @@ static int tiadc_probe(struct platform_device *pdev) err_dma: iio_device_unregister(indio_dev); -err_buffer_unregister: -err_free_channels: + return err; } @@ -671,9 +711,8 @@ static int __maybe_unused tiadc_suspend(struct device *dev) unsigned int idle; idle = tiadc_readl(adc_dev, REG_CTRL); - idle &= ~(CNTRLREG_TSCSSENB); - tiadc_writel(adc_dev, REG_CTRL, (idle | - CNTRLREG_POWERDOWN)); + idle &= ~(CNTRLREG_SSENB); + tiadc_writel(adc_dev, REG_CTRL, idle | CNTRLREG_POWERDOWN); return 0; } @@ -686,12 +725,12 @@ static int __maybe_unused tiadc_resume(struct device *dev) /* Make sure ADC is powered up */ restore = tiadc_readl(adc_dev, REG_CTRL); - restore &= ~(CNTRLREG_POWERDOWN); + restore &= ~CNTRLREG_POWERDOWN; tiadc_writel(adc_dev, REG_CTRL, restore); tiadc_step_config(indio_dev); am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, - adc_dev->buffer_en_ch_steps); + adc_dev->buffer_en_ch_steps); return 0; } @@ -699,6 +738,7 @@ static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume); static const struct of_device_id ti_adc_dt_ids[] = { { .compatible = "ti,am3359-adc", }, + { .compatible = "ti,am4372-adc", }, { } }; MODULE_DEVICE_TABLE(of, ti_adc_dt_ids); diff --git a/drivers/iio/adc/twl6030-gpadc.c b/drivers/iio/adc/twl6030-gpadc.c index c6416ad795ca..afdb59e0b526 100644 --- a/drivers/iio/adc/twl6030-gpadc.c +++ b/drivers/iio/adc/twl6030-gpadc.c @@ -900,7 +900,7 @@ static int twl6030_gpadc_probe(struct platform_device *pdev) ret = pdata->calibrate(gpadc); if (ret < 0) { - dev_err(&pdev->dev, "failed to read calibration registers\n"); + dev_err(dev, "failed to read calibration registers\n"); return ret; } @@ -914,14 +914,14 @@ static int twl6030_gpadc_probe(struct platform_device *pdev) ret = twl6030_gpadc_enable_irq(TWL6030_GPADC_RT_SW1_EOC_MASK); if (ret < 0) { - dev_err(&pdev->dev, "failed to enable GPADC interrupt\n"); + dev_err(dev, "failed to enable GPADC interrupt\n"); return ret; } ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, TWL6030_GPADCS, TWL6030_REG_TOGGLE1); if (ret < 0) { - dev_err(&pdev->dev, "failed to enable GPADC module\n"); + dev_err(dev, "failed to enable GPADC module\n"); return ret; } diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c index 198d2916266d..83bea5ef765d 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -1332,7 +1332,6 @@ static int xadc_probe(struct platform_device *pdev) xadc = iio_priv(indio_dev); xadc->ops = id->data; - xadc->irq = irq; init_completion(&xadc->completion); mutex_init(&xadc->mutex); spin_lock_init(&xadc->lock); @@ -1397,7 +1396,7 @@ static int xadc_probe(struct platform_device *pdev) } } - ret = devm_request_irq(dev, xadc->irq, xadc->ops->interrupt_handler, 0, + ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler, 0, dev_name(dev), indio_dev); if (ret) return ret; @@ -1407,7 +1406,7 @@ static int xadc_probe(struct platform_device *pdev) if (ret) return ret; - ret = xadc->ops->setup(pdev, indio_dev, xadc->irq); + ret = xadc->ops->setup(pdev, indio_dev, irq); if (ret) return ret; diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h index 8b80195725e9..7d78ce698967 100644 --- a/drivers/iio/adc/xilinx-xadc.h +++ b/drivers/iio/adc/xilinx-xadc.h @@ -67,7 +67,6 @@ struct xadc { spinlock_t lock; struct completion completion; - int irq; }; enum xadc_type { |