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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2025-06-09 23:56:30 +0100
committerBiju Das <biju.das.jz@bp.renesas.com>2025-06-12 19:42:28 +0100
commite2944dc6587f39c3eefb15ee607e700314230a0b (patch)
tree8b50fb9320265db04fa154cad519920917adaecf /drivers/net/wireless/iwlwifi/iwl-agn-lib.c
parent7c1e102ccf1d276bbaee2ddb601b0bdeb6eeaf5c (diff)
drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validationHEADfor-linux-nextdrm-misc-next
Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate supported display modes. On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as possible. To ensure compatibility with both RZ/G2L and RZ/V2H(P) SoCs, function pointers are introduced. Modify `rzg2l_mipi_dsi_startup()` to use `dphy_conf_clks` for clock configuration and `rzg2l_mipi_dsi_bridge_mode_valid()` to invoke `dphy_mode_clk_check` for mode validation. This change ensures proper operation across different SoC variants by allowing fine-grained control over clock configuration and mode validation. Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250609225630.502888-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-agn-lib.c')
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