diff options
Diffstat (limited to 'drivers/thunderbolt')
| -rw-r--r-- | drivers/thunderbolt/Kconfig | 18 | ||||
| -rw-r--r-- | drivers/thunderbolt/tb.c | 2 | ||||
| -rw-r--r-- | drivers/thunderbolt/tb.h | 9 | ||||
| -rw-r--r-- | drivers/thunderbolt/tunnel.c | 8 | ||||
| -rw-r--r-- | drivers/thunderbolt/usb4.c | 2 |
5 files changed, 33 insertions, 6 deletions
diff --git a/drivers/thunderbolt/Kconfig b/drivers/thunderbolt/Kconfig index db3b0bef48f4..1de579c44b08 100644 --- a/drivers/thunderbolt/Kconfig +++ b/drivers/thunderbolt/Kconfig @@ -18,6 +18,24 @@ menuconfig USB4 if USB4 +config USB4_PCIE_TUNNELING + bool "Allow PCI Express tunneling over USB4 fabric" + depends on PCI + default y + help + USB4 and Thunderbolt devices typically include PCIe switch + with a number of PCIe endpoints such as USB host controllers, + GPUs and network adapters. These are made available to the + host system through PCIe tunneling. These can use DMA and + therefore have access to the host memory which is typically + guarded by an IOMMU. This option allows disabling PCIe + tunneling completely. + + For devices to be usable it is recommended to say Y here. + + Note this only works with systems that use Software Based + Connection Manager (this is most USB4 hosts). + config USB4_DEBUGFS_WRITE bool "Enable write by debugfs to configuration spaces (DANGEROUS)" help diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c index 4a94cb406bdf..1740dd3eb5aa 100644 --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c @@ -3372,7 +3372,7 @@ struct tb *tb_probe(struct tb_nhi *nhi) if (!tb) return NULL; - if (tb_acpi_may_tunnel_pcie()) + if (tb_may_tunnel_pcie()) tb->security_level = TB_SECURITY_USER; else tb->security_level = TB_SECURITY_NOPCIE; diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h index 8e2762ff8d51..629c745c1399 100644 --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h @@ -1531,6 +1531,15 @@ static inline int tb_acpi_power_on_retimers(struct tb_port *port) { return 0; } static inline int tb_acpi_power_off_retimers(struct tb_port *port) { return 0; } #endif +static inline bool tb_may_tunnel_pcie(void) +{ +#ifdef CONFIG_USB4_PCIE_TUNNELING + return tb_acpi_may_tunnel_pcie(); +#else + return false; +#endif +} + #ifdef CONFIG_DEBUG_FS void tb_debugfs_init(void); void tb_debugfs_exit(void); diff --git a/drivers/thunderbolt/tunnel.c b/drivers/thunderbolt/tunnel.c index bfa0607b5574..7a8425699615 100644 --- a/drivers/thunderbolt/tunnel.c +++ b/drivers/thunderbolt/tunnel.c @@ -132,7 +132,7 @@ static unsigned int tb_available_credits(const struct tb_port *port, size_t ndp; usb3 = tb_acpi_may_tunnel_usb3() ? sw->max_usb3_credits : 0; - pcie = tb_acpi_may_tunnel_pcie() ? sw->max_pcie_credits : 0; + pcie = tb_may_tunnel_pcie() ? sw->max_pcie_credits : 0; if (tb_acpi_is_xdomain_allowed()) { spare = min_not_zero(sw->max_dma_credits, dma_credits); @@ -559,7 +559,7 @@ bool tb_tunnel_reserved_pci(struct tb_port *port, int *reserved_up, if (WARN_ON_ONCE(!port->remote)) return false; - if (!tb_acpi_may_tunnel_pcie()) + if (!tb_may_tunnel_pcie()) return false; if (tb_port_get_link_generation(port) < 4) @@ -1728,7 +1728,7 @@ static unsigned int tb_dma_available_credits(const struct tb_port *port) int credits; credits = tb_available_credits(port, NULL); - if (tb_acpi_may_tunnel_pcie()) + if (tb_may_tunnel_pcie()) credits -= sw->max_pcie_credits; credits -= port->dma_credits; @@ -2040,7 +2040,7 @@ static int tb_usb3_consumed_bandwidth(struct tb_tunnel *tunnel, int *consumed_up, int *consumed_down) { struct tb_port *port = tb_upstream_port(tunnel->dst_port->sw); - int pcie_weight = tb_acpi_may_tunnel_pcie() ? TB_PCI_WEIGHT : 0; + int pcie_weight = tb_may_tunnel_pcie() ? TB_PCI_WEIGHT : 0; /* * PCIe tunneling, if enabled, affects the USB3 bandwidth so diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c index 76f01713a875..4abbf0884fdd 100644 --- a/drivers/thunderbolt/usb4.c +++ b/drivers/thunderbolt/usb4.c @@ -279,7 +279,7 @@ int usb4_switch_setup(struct tb_switch *sw) * Only enable PCIe tunneling if the parent router supports it * and it is not disabled. */ - if (tb_acpi_may_tunnel_pcie() && + if (tb_may_tunnel_pcie() && tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) { val |= ROUTER_CS_5_PTO; /* |