diff options
| -rw-r--r-- | drivers/gpu/drm/tidss/tidss_dispc.c | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 8e2c8ecb9f18..27ac57d77032 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -609,13 +609,13 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport) #define VID_REG_GET(dispc, hw_plane, idx, mask) \ ((u32)FIELD_GET((mask), dispc_vid_read((dispc), (hw_plane), (idx)))) -#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ +#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, mask) \ ({ \ struct dispc_device *_dispc = (dispc); \ u32 _hw_plane = (hw_plane); \ u32 _idx = (idx); \ u32 _reg = dispc_vid_read(_dispc, _hw_plane, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \ }) @@ -1742,7 +1742,8 @@ static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(9, 9)); } /* SCALER */ @@ -1999,20 +2000,20 @@ static void dispc_vid_set_scaling(struct dispc_device *dispc, u32 fourcc) { /* HORIZONTAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_x, 7, 7); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_x, + GENMASK(7, 7)); /* VERTICAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_y, 8, 8); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_y, + GENMASK(8, 8)); /* Skip the rest if no scaling is used */ if (!sp->scale_x && !sp->scale_y) return; /* VERTICAL 5-TAPS */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->five_taps, 21, 21); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->five_taps, + GENMASK(21, 21)); if (dispc_fourcc_is_yuv(fourcc)) { if (sp->scale_x) { @@ -2102,7 +2103,7 @@ static void dispc_plane_set_pixel_format(struct dispc_device *dispc, if (dispc_color_formats[i].fourcc == fourcc) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, dispc_color_formats[i].dss_code, - 6, 1); + GENMASK(6, 1)); return; } } @@ -2280,15 +2281,16 @@ void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 28, 28); + GENMASK(28, 28)); else VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 28, 28); + GENMASK(28, 28)); } void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(0, 0)); } static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) @@ -2357,7 +2359,7 @@ static void dispc_k2g_plane_init(struct dispc_device *dispc) * register is ignored. */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 19, 19); + GENMASK(19, 19)); } } @@ -2408,7 +2410,7 @@ static void dispc_k3_plane_init(struct dispc_device *dispc) /* Prefech up to PRELOAD value */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 19, 19); + GENMASK(19, 19)); } } |