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authorVille Syrjälä <ville.syrjala@linux.intel.com>2025-09-17 23:34:43 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2025-09-18 23:41:47 +0300
commit6559ca4a42d7976497fcf49e4c4fad9639fc1f76 (patch)
treecef75b1c385495d9ab9e7e1d8d93cbe325347ed2
parenta0f8dd08a55b6a5c456c0124dc9a978aa65b651c (diff)
drm/i915/vrr: Readout framestart_delay earlier
In order to pretend that ICL/TGL VRR hardware has a similar guardband as on ADL+ we'll need access to framestart_delay already during intel_vrr_get_config(). Hoist the framestart_delay to an earlier point to make that possible. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250917203446.14374-3-ville.syrjala@linux.intel.com Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
-rw-r--r--drivers/gpu/drm/i915/display/intel_display.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a743d1339550..c7d85fd38890 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3891,6 +3891,15 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
intel_joiner_get_config(pipe_config);
intel_dsc_get_config(pipe_config);
+ if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
+ tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
+
+ pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
+ } else {
+ /* no idea if this is correct */
+ pipe_config->framestart_delay = 1;
+ }
+
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
DISPLAY_VER(display) >= 11)
intel_get_transcoder_timings(crtc, pipe_config);
@@ -3942,15 +3951,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1;
}
- if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
- tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
-
- pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
- } else {
- /* no idea if this is correct */
- pipe_config->framestart_delay = 1;
- }
-
out:
intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);