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2025-04-01Merge tag 'phy-for-6.15' of ↵Linus Torvalds30-230/+4190
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "A fairly moderate sized request for the generic phy subsystem with some new device and driver support along with driver updates with Samsung and Qualcomm ones being major ones. New HW Support: - Qualcomm X1P42100 PCIe Gen4x4, QCS615 qmp usbc, PCIe UNIPHY 28LP driver, SM8750 QMP UFS PHY - Rockchip rk3576 hdptx, rk3562 naneng-combo support - Samsung MIPI D-/C-PHY driver, ExynosAutov920 ufs phy driver Updates: - Samsung USB3 Type-C lane orientation detection and configuration for Google gs101 - Qualcomm support for dual lane PHY support for QCS8300 SoC" * tag 'phy-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (47 commits) phy: rockchip-naneng-combo: Support rk3562 dt-bindings: phy: rockchip: Add rk3562 naneng-combophy compatible phy: rockchip: Add Samsung MIPI D-/C-PHY driver dt-bindings: phy: Add Rockchip MIPI C-/D-PHY schema phy: qcom: uniphy-28lp: add COMMON_CLK dependency phy: rockchip: usbdp: Remove unnecessary bool conversion phy: rockchip: usbdp: Avoid call hpd_event_trigger in dp_phy_init phy: rockchip: usbdp: Only verify link rates/lanes/voltage when the corresponding set flags are set phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750 dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the SM8750 QMP UFS PHY phy: qcom: Introduce PCIe UNIPHY 28LP driver dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy phy: qcom: qmp-usbc: Add qmp configuration for QCS615 phy: freescale: imx8m-pcie: assert phy reset and perst in power off phy: freescale: imx8m-pcie: cleanup reset logic phy: core: Remove unused phy_pm_runtime_(allow|forbid) dt-bindings: phy: document Allwinner A523 USB-2.0 PHY phy: phy-rockchip-samsung-hdptx: Add support for RK3576 ...
2025-03-16phy: rockchip-naneng-combo: Support rk3562Jon Lin1-0/+152
rk3562 has 1 naneng comboPHY used for PCIe and USB3. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250227110836.2343158-2-kever.yang@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-16phy: rockchip: Add Samsung MIPI D-/C-PHY driverHeiko Stuebner3-0/+1732
Add driver for the MIPI D-/C-PHY block based around a Samsung IP-block that is for example needed to drive a MIPI DSI output on rk3588. Right now only the D-PHY portion is implemented, with the C-PHY part needing separate work. Tested-by: Daniel Semkowicz <dse@thaumatec.com> Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Link: https://lore.kernel.org/r/20250313134035.278133-3-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-16phy: qcom: uniphy-28lp: add COMMON_CLK dependencyArnd Bergmann1-0/+1
In configurations without CONFIG_COMMON_CLK, the driver fails to build: aarch64-linux-ld: drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.o: in function `qcom_uniphy_pcie_probe': phy-qcom-uniphy-pcie-28lp.c:(.text+0x200): undefined reference to `__clk_hw_register_fixed_rate' aarch64-linux-ld: phy-qcom-uniphy-pcie-28lp.c:(.text+0x238): undefined reference to `of_clk_hw_simple_get' phy-qcom-uniphy-pcie-28lp.c:(.text+0x238): dangerous relocation: unsupported relocation aarch64-linux-ld: phy-qcom-uniphy-pcie-28lp.c:(.text+0x240): undefined reference to `of_clk_hw_simple_get' aarch64-linux-ld: phy-qcom-uniphy-pcie-28lp.c:(.text+0x248): undefined reference to `devm_of_clk_add_hw_provider' Add that as a Kconfig dependencies. Fixes: 74badb8b0b14 ("phy: qcom: Introduce PCIe UNIPHY 28LP driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250314154915.4074980-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-12phy: rockchip: usbdp: Remove unnecessary bool conversionThorsten Blum1-1/+1
Remove the unnecessary bool conversion and simplify the code. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250224220339.199180-2-thorsten.blum@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-12phy: rockchip: usbdp: Avoid call hpd_event_trigger in dp_phy_initAndy Yan1-1/+0
Function rk_udphy_dp_hpd_event_trigger will set vogrf let it trigger HPD interrupt to DP by Type-C. This configuration is only required when the DP work in Alternate Mode, and called by typec_mux_set. In standard DP mode, such settings will prevent the DP from receiving HPD interrupts. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20250302115257.188774-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-12phy: rockchip: usbdp: Only verify link rates/lanes/voltage when the ↵Andy Yan1-34/+53
corresponding set flags are set According documentation of phy_configure_opts_dp, at the configure stage, link rates should only be verify/configure when set_rate flag is set, the same applies to lanes and voltage. So do it as the documentation says. Because voltage setting depends on the lanes, link rates set previously, so record the link rates and lanes at it's verify stage. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20250312080041.524546-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300Ziyue Zhang1-0/+89
The PCIe Gen4x2 PHY for qcs8300 has a lot of difference with sa8775p. So the qcs8300_qmp_gen4x2_pcie_rx_alt_tbl for qcs8300 is added. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> Link: https://lore.kernel.org/r/20250310063103.3924525-3-quic_ziyuzhan@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750Nitin Rawat3-8/+246
Add SM8750 specific register layout and table configs. The serdes TX RX register offset has changed for SM8750 and hence keep UFS specific serdes offsets in a dedicated header file. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250310-sm8750_ufs_master-v2-2-0dfdd6823161@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11phy: qcom: Introduce PCIe UNIPHY 28LP driverNitheesh Sekar3-0/+299
Add Qualcomm PCIe UNIPHY 28LP driver support present in Qualcomm IPQ5332 SoC and the phy init sequence. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250220094251.230936-3-quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11phy: qcom: qmp-usbc: Add qmp configuration for QCS615Krishna Kurapati1-0/+3
Provide PHY configuration for the USB QMP PHY for QCS615 Platform. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Unreviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250310110359.210990-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11phy: freescale: imx8m-pcie: assert phy reset and perst in power offStefan Eichenberger1-0/+11
Ensure the PHY reset and perst is asserted during power-off to guarantee it is in a reset state upon repeated power-on calls. This resolves an issue where the PHY may not properly initialize during subsequent power-on cycles. Power-on will deassert the reset at the appropriate time after tuning the PHY parameters. During suspend/resume cycles, we observed that the PHY PLL failed to lock during resume when the CPU temperature increased from 65C to 75C. The observed errors were: phy phy-32f00000.pcie-phy.3: phy poweron failed --> -110 imx6q-pcie 33800000.pcie: waiting for PHY ready timeout! imx6q-pcie 33800000.pcie: PM: dpm_run_callback(): genpd_resume_noirq+0x0/0x80 returns -110 imx6q-pcie 33800000.pcie: PM: failed to resume noirq: error -110 This resulted in a complete CPU freeze, which is resolved by ensuring the PHY is in reset during power-on, thus preventing PHY PLL failures. Cc: stable@vger.kernel.org Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250305144355.20364-3-eichest@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11phy: freescale: imx8m-pcie: cleanup reset logicStefan Eichenberger1-9/+3
Remove the switch statement and base perst release on whether it is found in the device tree. The probe function fails without the reset property, making it mandatory. Therefore, always release reset independent of the variant. This does not change the behavior of the driver but reduces driver complexity and allows for easier future modifications. Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250305144355.20364-2-eichest@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-10phy: core: Remove unused phy_pm_runtime_(allow|forbid)Dr. David Alan Gilbert1-24/+0
phy_pm_runtime_allow() and phy_pm_runtime_forbid() were added in 2013 as part of commit ff764963479a ("drivers: phy: add generic PHY framework") but have remained unused. Remove them. Fix up the (English) docs - I've left the Chinese translation. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Link: https://lore.kernel.org/r/20250306015408.277729-1-linux@treblig.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-10phy: phy-rockchip-samsung-hdptx: Add support for RK3576Nicolas Frattaroli1-0/+11
Despite the compatible already being listed in the bindings, the PHY driver never gained explicit support for it. This is especially a problem because the explicitly listed PHY addresses need to be specified for each SoC. To solve this, add the compatible, and a PHY config, with the address gleaned from rk3576.dtsi. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250306-rk3576-hdptx-phy-v1-1-288cc4b0611a@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-03Merge tag 'v6.14-rc5' of ↵Bartosz Golaszewski7-35/+73
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next Linux 6.14-rc5
2025-02-27phy: exynos5-usbdrd: Do not depend on Type-CKrzysztof Kozlowski1-1/+1
Older Exynos designs, like Exynos5422, do not have USB Type-C and the USB DRD PHY does not really need CONFIG_TYPEC for these devices at all. Incorrectly added optional dependency on CONFIG_TYPEC caused this driver to be missing for exynos_defconfig and as result Exynos5422-based boards like Hardkernel Odroid HC1 failed to probe USB. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Closes: https://krzk.eu/#/builders/21/builds/6139 Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Closes: https://lore.kernel.org/all/3c0b77e6-357d-453e-8b63-4757c3231bde@samsung.com/ Fixes: 09dc674295a3 ("phy: exynos5-usbdrd: subscribe to orientation notifier if required") Reviewed-by: André Draszik <andre.draszik@linaro.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250227070518.5468-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-17phy: mapphone-mdm6600: use gpiod_multi_set_value_cansleepDavid Lechner1-3/+1
Reduce verbosity by using gpiod_multi_set_value_cansleep() instead of gpiod_set_array_value_cansleep(). ddata->cmd_gpios->ndescs is validated to be equal to PHY_MDM6600_NR_CMD_LINES during driver probe, so it will have the same value as the previously hard-coded argument. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: David Lechner <dlechner@baylibre.com> Acked-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20250210-gpio-set-array-helper-v3-14-d6a673674da8@baylibre.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-02-14phy: PHY_LAN966X_SERDES should depend on SOC_LAN966 || MCHP_LAN966X_PCIGeert Uytterhoeven1-0/+1
The Microchip LAN966X SerDes PHY is only present on Microchip LAN966x SoCs. However, when used as a PCI endpoint, all peripherals of the LAN966x SoC can be accessed by the PCI host. Hence add dependencies on SOC_LAN966 and MCHP_LAN966X_PCI, to prevent asking the user about this driver when configuring a kernel without Microchip LAN966x SoC and PCIe support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/369233dfded88ff6fb342e03794fe31985d84d82.1737383314.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-14phy: tegra: xusb: reset VBUS & ID OVERRIDEBH Hsieh1-0/+11
Observed VBUS_OVERRIDE & ID_OVERRIDE might be programmed with unexpected value prior to XUSB PADCTL driver, this could also occur in virtualization scenario. For example, UEFI firmware programs ID_OVERRIDE=GROUNDED to set a type-c port to host mode and keeps the value to kernel. If the type-c port is connected a usb host, below errors can be observed right after usb host mode driver gets probed. The errors would keep until usb role class driver detects the type-c port as device mode and notifies usb device mode driver to set both ID_OVERRIDE and VBUS_OVERRIDE to correct value by XUSB PADCTL driver. [ 173.765814] usb usb3-port2: Cannot enable. Maybe the USB cable is bad? [ 173.765837] usb usb3-port2: config error Taking virtualization into account, asserting XUSB PADCTL reset would break XUSB functions used by other guest OS, hence only reset VBUS & ID OVERRIDE of the port in utmi_phy_init. Fixes: bbf711682cd5 ("phy: tegra: xusb: Add Tegra186 support") Cc: stable@vger.kernel.org Change-Id: Ic63058d4d49b4a1f8f9ab313196e20ad131cc591 Signed-off-by: BH Hsieh <bhsieh@nvidia.com> Signed-off-by: Henry Lin <henryl@nvidia.com> Link: https://lore.kernel.org/r/20250122105943.8057-1-henryl@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-14phy: ti: gmii-sel: Do not use syscon helper to build regmapAndrew Davis1-1/+14
The syscon helper device_node_to_regmap() is used to fetch a regmap registered to a device node. It also currently creates this regmap if the node did not already have a regmap associated with it. This should only be used on "syscon" nodes. This driver is not such a device and instead uses device_node_to_regmap() on its own node as a hacky way to create a regmap for itself. This will not work going forward and so we should create our regmap the normal way by defining our regmap_config, fetching our memory resource, then using the normal regmap_init_mmio() function. Signed-off-by: Andrew Davis <afd@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20250123182234.597665-1-afd@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-14phy: exynos5-usbdrd: gs101: ensure power is gated to SS phy in phy_exit()André Draszik1-5/+8
We currently don't gate the power to the SS phy in phy_exit(). Shuffle the code slightly to ensure the power is gated to the SS phy as well. Fixes: 32267c29bc7d ("phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)") CC: stable@vger.kernel.org # 6.11+ Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20241205-gs101-usb-phy-fix-v4-1-0278809fb810@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-14phy: fsl-imx8mq-usb: add tca function driver for imx95Xu Yang2-0/+241
The i.MX95 USB3 phy has a Type-C Assist block (TCA). This block consists two functional blocks (XBar assist and VBus assist) and one system access interface using APB. The primary functionality of XBar assist is: - switching lane for flip - moving unused lanes into lower power states. This info can be get from: i.MX95 RM Chapter 163.3.8 Type-C assist (TCA) block. This will add support for TCA block to achieve lane switching and tca lower power functionality. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> Link: https://lore.kernel.org/r/20241204050907.1081781-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: samsung-ufs: support ExynosAutov920 ufs phy driverSowon Na4-3/+179
Add support for ExynosAutov920 ufs phy driver. Signed-off-by: Sowon Na <sowon.na@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20241226031142.1764652-3-sowon.na@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: phy-rockchip-samsung-hdptx: Add eDP mode support for RK3588Damon Ding1-10/+869
The PHY is based on a Samsung IP block that supports HDMI 2.1, and eDP 1.4b. RK3588 integrates the Analogix eDP 1.3 TX controller IP and the HDMI/eDP TX Combo PHY to support eDP display. Add basic support for RBR/HBR/HBR2 link rates, and the voltage swing and pre-emphasis configurations of each link rate are set according to the eDP 1.3 requirements. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250205105157.580060-5-damon.ding@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: phy-rockchip-samsung-hdptx: Add the '_MASK' suffix to all registersDamon Ding1-44/+44
Adding the '_MASK' suffix to all registers in order to ensures consistency in the naming convention for register macros throughout the file. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250205105157.580060-4-damon.ding@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: phy-rockchip-samsung-hdptx: Supplement some register names with their ↵Damon Ding1-3/+3
full version Complete the register names of CMN_REG(0081) and CMN_REG(0087) to their full version, and it can help to better match the datasheet. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250205105157.580060-3-damon.ding@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: phy-rockchip-samsung-hdptx: Swap the definitions of LCPLL_REF and ROPLL_REFDamon Ding1-2/+2
According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097) to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0 selects the ROPLL. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250205105157.580060-2-damon.ding@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: freescale: fsl-samsung-hdmi: Use helper function devm_clk_get_enabled()Pei Xiao1-9/+1
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly. Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn> Link: https://lore.kernel.org/r/tencent_9087BCE04E38E6AA5C4B2252B82FA99C2009@qq.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: core: don't require set_mode() callback for phy_get_mode() to workDmitry Baryshkov1-3/+4
As reported by Damon Ding, the phy_get_mode() call doesn't work as expected unless the PHY driver has a .set_mode() call. This prompts PHY drivers to have empty stubs for .set_mode() for the sake of being able to get the mode. Make .set_mode() callback truly optional and update PHY's mode even if it there is none. Cc: Damon Ding <damon.ding@rock-chips.com> Link: https://lore.kernel.org/r/96f8310f-93f1-4bcb-8637-137e1159ff83@rock-chips.com Tested-by: Damon Ding <damon.ding@rock-chips.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250209-phy-fix-set-moe-v2-1-76e248503856@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: freescale: fsl-samsung-hdmi: Limit PLL lock detection clock divider to ↵Pei Xiao1-2/+11
valid range FIELD_PREP() checks that a value fits into the available bitfield, but the index div equals to 4,is out of range. which gcc complains about: In function ‘fsl_samsung_hdmi_phy_configure_pll_lock_det’, inlined from ‘fsl_samsung_hdmi_phy_configure’ at drivers/phy/freescale/phy-fsl-samsung-hdmi.c :470:2: ././include/linux/compiler_types.h:542:38: error: call to ‘__compiletime_assert_538’ declared with attribute error: FIELD_PREP: value too large for the field 542 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ ././include/linux/compiler_types.h:523:4: note: in definition of macro ‘__compiletime_assert’ 523 | prefix ## suffix(); | ^~~~~~ ././include/linux/compiler_types.h:542:2: note: in expansion of macro ‘_compiletime_assert’ 542 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) REG12_CK_DIV_MASK only two bit, limit div to range 0~3, so build error will fix. Fixes: d567679f2b6a ("phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation") Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn> Changlog: Reviewed-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/tencent_6F503D43467AA99DD8CC59B8F645F0725B0A@qq.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: stih407-usb: Use syscon_regmap_lookup_by_phandle_argsKrzysztof Kozlowski1-17/+7
Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over syscon_regmap_lookup_by_phandle() combined with getting the syscon argument. Except simpler code this annotates within one line that given phandle has arguments, so grepping for code would be easier. There is also no real benefit in printing errors on missing syscon argument, because this is done just too late: runtime check on static/build-time data. Dtschema and Devicetree bindings offer the static/build-time check for this already. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250111185407.183855-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)André Draszik1-8/+42
To make USB runtime suspend work when a UDC has been bound, the phy needs to inform the USBDRD controller (DWC3) that Vbus and bvalid are gone, so that it can in turn raise the respective gadget interrupt with event == DWC3_DEVICE_EVENT_DISCONNECT, which will cause the USB stack to clean up, allowing DWC3 to enter runtime suspend. On e850 and gs101 this isn't working, as the respective signals are not directly connected, and instead this driver uses override bits in the PHY IP to set those signals. It currently forcefully sets them to 'on', so the above mentioned interrupt will not be raised, preventing runtime suspend. To detect that state, update this driver to act on the TCPC's orientation signal - when orientation == NONE, Vbus is gone and we can clear the respective bits. Similarly, for other orientation values we re-enable them. This makes runtime suspend work on platforms with a TCPC (like Pixel6), while keeping compatibility with platforms without (e850-96). With runtime suspend working, USB-C cable orientation detection now also fully works on such platforms, and the link comes up as Superspeed as expected irrespective of the cable orientation and whether UDC / gadget are configured and active. Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-7-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: subscribe to orientation notifier if requiredAndré Draszik2-0/+57
gs101's SS phy needs to be configured differently based on the connector orientation, as the SS link can only be established if the mux is configured correctly. The code to handle programming of the mux is in place already, this commit now adds the missing pieces to subscribe to the Type-C orientation switch event. Note that for this all to work we rely on the USB controller re-initialising us. It should invoke our .exit() upon cable unplug, and during cable plug we'll receive the orientation event after which we expect our .init() to be called. Above reinitialisation happens if the DWC3 controller can enter runtime suspend automatically. For the DWC3 driver, this is an opt-in: echo auto > /sys/devices/.../11110000.usb/power/control Once done, things work as long as the UDC is not bound as otherwise it stays busy because it doesn't cancel / stop outstanding TRBs. For now we have to manually unbind the UDC in that case: echo "" > sys/kernel/config/usb_gadget/.../UDC Note that if the orientation-switch property is missing from the DT, the code will behave as before this commit (meaning for gs101 it will work in SS mode in one orientation only). Other platforms are not affected either way. Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-6-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: gs101: configure SS lanes based on orientationAndré Draszik1-21/+51
USB SS lanes need to be configured based on the connector orientation - at most two lanes will be in use for USB (and the remaining two for alternate modes like DP). For the USB link to come up in SS, the lane configuration registers have to be programmed accordingly. While we still need a way to be notified of the actual connector orientation and then reprogram the registers accordingly (at the moment the configuration happens just once during phy_init() and never again), we can prepare the code doing the configuration to take the orientation into account. Do so. Note: the mutex is needed to synchronize this with the upcoming connector orientation callback. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-5-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: fix EDS distribution tuning (gs101)André Draszik1-2/+5
This code's intention is to configure lane0 and lane2 tunings, but for lane2 there is a typo and it ends up tuning something else. Fix the typo, as it doesn't appear to make sense to apply different tunings for lane0 vs lane2. The same typo appears to exist in the bootloader, hence we restore the original value in the typo'd registers as well. This can be removed once / if the bootloader is updated. Note that this is incorrect in the downstream driver as well - the values had been copied from there. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-4-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: convert to dev_err_probeAndré Draszik1-12/+9
dev_err_probe() exists to simplify code. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-3-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: Use (of|device)_property_present() for non-boolean propertiesRob Herring (Arm)2-4/+4
The use of (of|device)_property_read_bool() for non-boolean properties is deprecated in favor of (of|device)_property_present() when testing for property presence. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20241231163121.241543-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: can-transceiver: Drop unnecessary "mux-states" property presence checkRob Herring (Arm)1-7/+6
It doesn't matter whether "mux-states" is not present or there is some other issue parsing it causing an error. Drop the presence check and rework the error handling to ignore anything other than deferred probe. Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250203185421.3383805-2-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHYKonrad Dybcio1-0/+18
Add a new, common configuration for Gen4x4 V6 PHYs without an init sequence. The bootloader configures the hardware once and the OS retains that configuration by using the NOCSR reset line (which doesn't drop register state on assert) in place of the "full reset" one. Use this new configuration for X1P42100's Gen4x4 PHY. Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-3-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: phy-rockchip-samsung-hdptx: Don't use dt aliases to determine phy-idHeiko Stuebner1-6/+44
The phy needs to know its identity in the system (phy0 or phy1 on rk3588) for some actions and the driver currently contains code abusing of_alias for that. Devicetree aliases are always optional and should not be used for core device functionality, so instead keep a list of phys on a soc in the of_device_data and find the phy-id by comparing against the mapped register-base. Fixes: c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support") Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241206103401.1780416-3-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: phy-rockchip-samsung-hdptx: annotate regmap register-callbackHeiko Stuebner1-7/+7
The variant of the driver in the vendor-tree contained those handy comments in the regmap register callback. Having the different ranges describe what they are looks helpful. Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241206103401.1780416-2-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclkKaustabh Chakraborty1-6/+6
In exynos5_usbdrd_{pipe3,utmi}_set_refclk(), the masks PHYCLKRST_MPLL_MULTIPLIER_MASK and PHYCLKRST_SSC_REFCLKSEL_MASK are not inverted when applied to the register values. Fix it. Cc: stable@vger.kernel.org Fixes: 59025887fb08 ("phy: Add new Exynos5 USB 3.0 PHY driver") Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20250209-exynos5-usbdrd-masks-v1-1-4f7f83f323d7@disroot.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: stm32: Fix constant-value overflow assertionChristian Bruel1-20/+18
Rework the workaround as the lookup tables always fits into the bitfield, and the default values are defined by the hardware and cannot be 0: Guard against false positive with a WARN_ON check to make the compiler happy: The offset range is pre-checked against the sorted imp_lookup_table values and overflow should not happen and would be caught by a warning and return in error. Also guard against a true positive found during the max_vswing lookup, as a max vswing value can be 802000 or 803000 microvolt depending on the current impedance. Therefore set the default impedence index. Fixes: 2de679ecd724 ("phy: stm32: work around constant-value overflow assertion") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250210103515.2598377-1-christian.bruel@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-04phy: rockchip: naneng-combphy: compatible reset with old DTChukun Pan1-1/+4
The device tree of RK3568 did not specify reset-names before. So add fallback to old behaviour to be compatible with old DT. Fixes: fbcbffbac994 ("phy: rockchip: naneng-combphy: fix phy reset") Cc: Jianfeng Liu <liujianfeng1994@gmail.com> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250106100001.1344418-2-amadeus@jmu.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-04phy: rockchip: fix Kconfig dependency moreArnd Bergmann1-0/+1
A previous patch ensured that USB Type C connector support is enabled, but it is still possible to build the phy driver without enabling CONFIG_USB (host support) or CONFIG_USB_GADGET (device support), and in that case the common helper functions are unavailable: aarch64-linux-ld: drivers/phy/rockchip/phy-rockchip-usbdp.o: in function `rk_udphy_probe': phy-rockchip-usbdp.c:(.text+0xe74): undefined reference to `usb_get_maximum_speed' Select CONFIG_USB_COMMON directly here, like we do in some other phy drivers, to make sure this is available even when actual USB support is disabled or in a loadable module that cannot be reached from a built-in phy driver. Fixes: 9c79b779643e ("phy: rockchip: fix CONFIG_TYPEC dependency") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250122065249.1390081-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-01-29Merge tag 'phy-for-6.14' of ↵Linus Torvalds25-164/+895
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "Lots of Qualcomm and Rockchip device support. New Support: - Qualcomm SAR2130P qmp usb, SAR2130P qmp pcie, QCS615 qusb2 and PCIe, IPQ5424 qmp pcie, IPQ5424 QUSB2 and USB3 PHY - Rockchip rk3576 combo phy support Updates: - Drop Shengyang for JH7110 maintainer - Freescale hdmi register calculation optimization - Rockchip pcie phy mutex and regmap updates" * tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (37 commits) dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY phy: rockchip: phy-rockchip-typec: Fix Copyright description dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs phy: qcom-qusb2: Add support for QCS615 dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings phy: core: Simplify API of_phy_simple_xlate() implementation phy: sun4i-usb: Remove unused of_gpio.h phy: HiSilicon: Don't use "proxy" headers phy: samsung-ufs: switch back to syscon_regmap_lookup_by_phandle() phy: qualcomm: qmp-pcie: add support for SAR2130P phy: qualcomm: qmp-pcie: define several new registers phy: qualcomm: qmp-pcie: split PCS_LANE1 region phy: qualcomm: qmp-combo: add support for SAR2130P dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SAR2130P compatible dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add SAR2130P compatible phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found phy: freescale: fsl-samsung-hdmi: Expand Integer divider range phy: rockchip-naneng-combo: add rk3576 support dt-bindings: phy: rockchip: add rk3576 compatible ...
2025-01-15mediatek: stop messing with ->d_inameAl Viro1-30/+10
use debgufs_{create_file,get}_aux_num() instead. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Link: https://lore.kernel.org/r/20250112080705.141166-11-viro@zeniv.linux.org.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-25phy: rockchip: phy-rockchip-typec: Fix Copyright descriptionAndy Yan1-1/+1
The company name has update to Rockchip Electronics Co., Ltd. since 2021. And change Co.Ltd to Co., Ltd. to fix mail server warning: DBL_SPAM(6.50)[co.ltd:url]; Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241216100739.3726293-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: mediatek: phy-mtk-hdmi: add regulator dependencyArnd Bergmann1-0/+1
The driver no longer builds when regulator support is unavailable: arm-linux-gnueabi-ld: drivers/phy/mediatek/phy-mtk-hdmi.o: in function `mtk_hdmi_phy_register_regulators': phy-mtk-hdmi.c:(.text.unlikely+0x3e): undefined reference to `devm_regulator_register' arm-linux-gnueabi-ld: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.o: in function `mtk_hdmi_phy_pwr5v_is_enabled': phy-mtk-hdmi-mt8195.c:(.text+0x326): undefined reference to `rdev_get_drvdata' arm-linux-gnueabi-ld: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.o: in function `mtk_hdmi_phy_pwr5v_disable': phy-mtk-hdmi-mt8195.c:(.text+0x346): undefined reference to `rdev_get_drvdata' arm-linux-gnueabi-ld: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.o: in function `mtk_hdmi_phy_pwr5v_enable': Fixes: 49393b2da1cd ("phy: mediatek: phy-mtk-hdmi: Register PHY provided regulator") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241213083056.2596499-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-11 21:39:17 +0000